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//////////////////////////////////////////////////////////////////////////////
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// //
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// Minimalistic 1-wire (onewire) master with Avalon MM bus interface //
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// testbench //
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// //
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// Copyright (C) 2010 Iztok Jeras //
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// //
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//////////////////////////////////////////////////////////////////////////////
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// //
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// This RTL is free hardware: you can redistribute it and/or modify //
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// it under the terms of the GNU Lesser General Public License //
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// as published by the Free Software Foundation, either //
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// version 3 of the License, or (at your option) any later version. //
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// //
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// This RTL is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with this program. If not, see <http://www.gnu.org/licenses/>. //
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// //
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module onewire_tb;
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localparam DEBUG = 1'b0;
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// system clock parameters
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localparam real FRQ = 6_000_000; // frequency 6MHz
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localparam real TCP = (10.0**9)/FRQ; // time clock period in ns
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`ifdef CDR_E
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localparam CDR_E = 1;
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`else
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localparam CDR_E = 0;
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`endif
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`ifdef PRESET_50_10
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localparam OVD_E = 1'b1; // overdrive functionality enable
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localparam BTP_N = "5.0"; // normal mode
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localparam BTP_O = "1.0"; // overdrive mode
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`elsif PRESET_60_05
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localparam OVD_E = 1'b1; // overdrive functionality enable
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localparam BTP_N = "6.0"; // normal mode
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localparam BTP_O = "0.5"; // overdrive mode
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`elsif PRESET_75
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localparam OVD_E = 1'b0; // overdrive functionality enable
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localparam BTP_N = "7.5"; // normal mode
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localparam BTP_O = "1.0"; // overdrive mode
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`else // default
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localparam OVD_E = 1'b1; // overdrive functionality enable
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localparam BTP_N = "5.0"; // normal mode
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localparam BTP_O = "1.0"; // overdrive mode
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`endif
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// port width parameters
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`ifdef BDW_32
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localparam BDW = 32; // 32bit bus data width
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`elsif BDW_8
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localparam BDW = 8; // 8bit bus data width
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`else // default
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localparam BDW = 32; // bus data width
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`endif
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// number of wires
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`ifdef OWN
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localparam OWN = `OWN; // number of wires
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`else
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localparam OWN = 3; // slaves with different timing (min, typ, max)
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`endif
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// computed bus address port width
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localparam BAW = (BDW==32) ? 1 : 2;
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// clock dividers for normal and overdrive mode
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// NOTE! must be round integer values
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`ifdef PRESET_60_05
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// there is no way to cast a real value into an integer
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localparam integer CDR_N = 45 - 1;
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localparam integer CDR_O = 4 - 1;
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`else
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localparam integer CDR_N = ((BTP_N == "5.0") ? 5.0 : 7.5 ) * FRQ / 1_000_000 - 1;
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localparam integer CDR_O = ((BTP_O == "1.0") ? 1.0 : 0.67) * FRQ / 1_000_000 - 1;
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`endif
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// Avalon MM parameters
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localparam AAW = BAW; // address width
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localparam ADW = BDW; // data width
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localparam ABW = ADW/8; // byte enable width
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// system_signals
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reg clk; // clock
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reg rst; // reset (asynchronous)
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// Avalon MM interface
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reg avalon_read;
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reg avalon_write;
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reg [AAW-1:0] avalon_address;
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reg [ABW-1:0] avalon_byteenable;
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reg [ADW-1:0] avalon_writedata;
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wire [ADW-1:0] avalon_readdata;
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wire avalon_waitrequest;
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wire avalon_interrupt;
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// Avalon MM local signals
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wire avalon_transfer;
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reg [BDW-1:0] data;
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// onewire
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wire [OWN-1:0] owr; // bidirectional
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wire [OWN-1:0] owr_p; // output power enable from master
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wire [OWN-1:0] owr_e; // output pull down enable from master
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wire [OWN-1:0] owr_i; // input into master
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// slave conviguration
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reg slave_ena; // slave enable (connect/disconnect from wire)
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reg [3:0] slave_sel; // 1-wire slave select
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reg slave_ovd; // overdrive mode enable
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reg slave_dat_r; // read data
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wire [OWN-1:0] slave_dat_w; // write data
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// error checking
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integer error;
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integer n;
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// overdrive enable loop
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integer i;
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//////////////////////////////////////////////////////////////////////////////
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// configuration printout and waveforms
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//////////////////////////////////////////////////////////////////////////////
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// request for a dumpfile
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initial begin
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$dumpfile("onewire.vcd");
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$dumpvars(0, onewire_tb);
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end
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// print configuration
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initial begin
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$display ("NOTE: Ports : BDW=%0d, BAW=%0d, OWN=%0d", BDW, BAW, OWN);
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$display ("NOTE: Clock : FRQ=%3.2fMHz, TCP=%3.2fns", FRQ/1_000_000.0, TCP);
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$display ("NOTE: Divide: CDR_E=%0b, CDR_N=%0d, CDR_O=%0d", CDR_E, CDR_N, CDR_O);
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$display ("NOTE: Config: OVD_E=%0b, BTP_N=%1.2fus, BTP_O=%1.2fus",
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OVD_E, (CDR_N+1)*1_000_000/FRQ, (CDR_O+1)*1_000_000/FRQ);
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end
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//////////////////////////////////////////////////////////////////////////////
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// clock and reset
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//////////////////////////////////////////////////////////////////////////////
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// clock generation
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initial clk = 1'b1;
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always #(TCP/2) clk = ~clk;
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// reset generation
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initial begin
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rst = 1'b1;
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repeat (2) @(posedge clk);
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rst = 1'b0;
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end
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//////////////////////////////////////////////////////////////////////////////
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// Avalon write and read transfers
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//////////////////////////////////////////////////////////////////////////////
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initial begin
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// reset error counter
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error = 0;
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// Avalon MM interface is idle
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avalon_read = 1'b0;
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avalon_write = 1'b0;
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// long delay to skip presence pulse
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slave_ena = 1'b0;
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#1000_000;
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// set clock divider ratios
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if (CDR_E) begin
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if (BDW==32) begin
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avalon_cycle (1, 1, 4'hf, { 16'h0001, 16'h0001}, data);
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avalon_cycle (1, 1, 4'hf, {CDR_O[15:0], CDR_N[15:0]}, data);
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end else if (BDW==8) begin
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avalon_cycle (1, 2, 1'b1, 8'h01, data);
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avalon_cycle (1, 3, 1'b1, 8'h01, data);
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avalon_cycle (1, 2, 1'b1, CDR_N[7:0], data);
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avalon_cycle (1, 3, 1'b1, CDR_O[7:0], data);
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end
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end
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// test with slaves with different timing (each slave one one of the wires)
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for (slave_sel=0; slave_sel<OWN; slave_sel=slave_sel+1) begin
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// select normal/overdrive mode
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//for (slave_ovd=0; slave_ovd<(OVD_E?2:1); slave_ovd=slave_ovd+1) begin
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for (i=0; i<(OVD_E?2:1); i=i+1) begin
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slave_ovd = i[0];
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// testbench status message
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$display("NOTE: Loop: speed=%s, ovd=%b, BTP=\"%s\")", (slave_sel==0) ? "typ" : (slave_sel==1) ? "min" : "max", slave_ovd, slave_ovd ? BTP_O : BTP_N);
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// generate a reset pulse
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slave_ena = 1'b0;
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slave_dat_r = 1'b1;
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avalon_request (16'd0, slave_sel, {slave_ovd, 2'b10});
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avalon_polling (8, n);
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// expect no response
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if (data[0] !== 1'b1) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong presence detect responce ('1' expected).", $time);
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end
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// generate a reset pulse
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slave_ena = 1'b1;
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slave_dat_r = 1'b1;
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avalon_request (16'd0, slave_sel, {slave_ovd, 2'b10});
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avalon_polling (8, n);
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// expect presence response
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if (data[0] !== 1'b0) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong presence detect response ('0' expected).", $time);
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end
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// write '0'
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slave_ena = 1'b1;
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slave_dat_r = 1'b1;
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avalon_request (16'd0, slave_sel, {slave_ovd, 2'b00});
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avalon_polling (8, n);
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// check if '0' was written into the slave
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if (slave_dat_w[slave_sel] !== 1'b0) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong write data for write '0'.", $time);
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end
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// check if '0' was read from the slave
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if (data[0] !== 1'b0) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong read data for write '0'.", $time);
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end
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// write '1', read '1'
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slave_ena = 1'b1;
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slave_dat_r = 1'b1;
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avalon_request (16'd0, slave_sel, {slave_ovd, 2'b01});
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avalon_polling (8, n);
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// check if '0' was written into the slave
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if (slave_dat_w[slave_sel] !== 1'b1) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong write data for write '1', read '1'.", $time);
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end
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// check if '1' was read from the slave
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if (data[0] !== 1'b1) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong read data for write '1', read '1'.", $time);
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end
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// write '1', read '0'
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slave_ena = 1'b1;
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slave_dat_r = 1'b0;
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avalon_request (16'd0, slave_sel, {slave_ovd, 2'b01});
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avalon_polling (8, n);
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// check if '0' was written into the slave
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if (slave_dat_w[slave_sel] !== 1'b0) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong write data for write '1', read '0'.", $time);
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end
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// check if '0' was read from the slave
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if (data[0] !== 1'b0) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong read data for write '1', read '0'.", $time);
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end
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end // slave_ovd
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end // slave_sel
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// test power supply on a typical normal mode slave
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slave_sel = 0;
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// generate a delay pulse (1ms) with power supply enabled
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avalon_request (16'd1, slave_sel, 3'b011);
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avalon_polling (1, n);
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// check if '1' was read from the slave
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if ((data[0] !== 1'b1) & ~slave_ovd) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong presence detect response (power expected).", $time);
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end
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// check if power is present
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if (owr_p[slave_sel] !== 1'b1) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong line power state", $time);
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end
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// check the time to run a delay cycle
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if ((n-1)*2 != FRQ/1000) begin
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$display("WARNING: (t=%0t) Non ideal cycle time (%0dus), should be around 1ms.", $time, 2*(n-1)*1_000_000/FRQ);
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end
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// generate a idle pulse (0ms) with power supply enabled
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avalon_request (16'd1, slave_sel, 3'b111);
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avalon_polling (1, n);
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// check if power is present
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if (owr_p[slave_sel] !== 1'b1) begin
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error = error+1;
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$display("ERROR: (t=%0t) Wrong line power state", $time);
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end
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// check the time to run an idle cycle
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if (n>1) begin
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$display("ERROR: (t=%0t) Non ideal idle cycle time, should be around zero.", $time);
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end
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// generate a delay pulse and break it with an idle pulse, before it finishes
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repeat (10) @(posedge clk);
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avalon_request (16'd0, 4'h0, 3'b011);
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repeat (10) @(posedge clk);
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avalon_request (16'd0, 4'h0, 3'b111);
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// wait a few cycles and finish
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repeat (10) @(posedge clk);
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$finish();
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end
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// avalon request cycle
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task avalon_request (
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input [15:0] pwr, // power enable
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input [3:0] sel, // onewire slave select
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input [2:0] cmd // command {ovd, rst, dat}
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);
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reg [BDW-1:0] data; // read data
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begin
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if (BDW==32) begin
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avalon_cycle (1, 0, 4'hf, {pwr<<sel, 4'h0, sel, 3'b000, pwr[0], 1'b1, cmd}, data);
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end else begin
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avalon_cycle (1, 1, 1'b1, {pwr[3:0]<<sel, 2'h0, sel[1:0]}, data);
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avalon_cycle (1, 0, 1'b1, { 3'b000, pwr[0], 1'b1, cmd}, data);
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end
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end endtask
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// wait for the onewire cycle completion
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task avalon_polling (
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input integer dly,
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output integer n
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); begin
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// set cycle counter to zero
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n = 0;
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// poll till owr_cyc ends
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if (BDW==32) begin
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data = 32'h08;
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while (data & 32'h08) begin
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repeat (dly) @ (posedge clk);
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avalon_cycle (0, 0, 4'hf, 32'hxxxx_xxxx, data);
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n = n + 1;
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end
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end else begin
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data = 8'h08;
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while (data & 8'h08) begin
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repeat (dly) @ (posedge clk);
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avalon_cycle (0, 0, 1'b1, 8'hxx, data);
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n = n + 1;
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end
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end
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end endtask
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//////////////////////////////////////////////////////////////////////////////
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// Avalon transfer cycle generation task
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//////////////////////////////////////////////////////////////////////////////
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task automatic avalon_cycle (
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input r_w, // 0-read or 1-write cycle
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input [AAW-1:0] adr,
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input [ABW-1:0] ben,
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input [ADW-1:0] wdt,
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output [ADW-1:0] rdt
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);
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begin
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if (DEBUG) $display ("Avalon MM cycle start: T=%10tns, %s address=%08x byteenable=%04b writedata=%08x", $time/1000.0, r_w?"write":"read ", adr, ben, wdt);
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// start an Avalon cycle
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avalon_read <= ~r_w;
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avalon_write <= r_w;
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avalon_address <= adr;
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avalon_byteenable <= ben;
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avalon_writedata <= wdt;
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// wait for waitrequest to be retracted
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@ (posedge clk); while (~avalon_transfer) @ (posedge clk);
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// end Avalon cycle
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avalon_read <= 1'b0;
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avalon_write <= 1'b0;
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// read data
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rdt = avalon_readdata;
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if (DEBUG) $display ("Avalon MM cycle end : T=%10tns, readdata=%08x", $time/1000.0, rdt);
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end
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endtask
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// avalon cycle transfer cycle end status
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assign avalon_transfer = (avalon_read | avalon_write) & ~avalon_waitrequest;
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assign avalon_waitrequest = 1'b0;
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//////////////////////////////////////////////////////////////////////////////
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// RTL instance
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//////////////////////////////////////////////////////////////////////////////
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sockit_owm #(
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.OVD_E (OVD_E),
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.CDR_E (CDR_E),
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.BDW (BDW ),
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.BAW (BAW ),
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.OWN (OWN ),
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.BTP_N (BTP_N),
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.BTP_O (BTP_O),
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.CDR_N (CDR_N),
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.CDR_O (CDR_O)
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) onewire_master (
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// system
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.clk (clk),
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.rst (rst),
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// Avalon
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.bus_ren (avalon_read),
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.bus_wen (avalon_write),
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.bus_adr (avalon_address),
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.bus_wdt (avalon_writedata),
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.bus_rdt (avalon_readdata),
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.bus_irq (avalon_interrupt),
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// onewire
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.owr_p (owr_p),
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.owr_e (owr_e),
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.owr_i (owr_i)
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);
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// pullup
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pullup onewire_pullup [OWN-1:0] (owr);
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// tristate buffers
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bufif1 onewire_buffer [OWN-1:0] (owr, owr_p, owr_e | owr_p);
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// read back
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assign owr_i = owr;
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//////////////////////////////////////////////////////////////////////////////
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// Verilog onewire slave models
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//////////////////////////////////////////////////////////////////////////////
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`ifdef OWN
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// fast slave device
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onewire_slave_model onewire_slave [OWN-1:0] (
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// configuration
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.ena (slave_ena),
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.ovd (slave_ovd),
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.dat_r (slave_dat_r),
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.dat_w (slave_dat_w),
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// 1-wire signal
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.owr (owr)
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);
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`else
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// Verilog onewire slave models for normal mode
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// typical slave device
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onewire_slave_model #(
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.TS (30)
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) onewire_slave_n_typ (
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// configuration
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.ena (slave_ena & (slave_ovd==0)),
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.ovd (slave_ovd ),
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.dat_r (slave_dat_r ),
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.dat_w (slave_dat_w[0]),
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// 1-wire signal
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.owr (owr[0])
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);
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// fast slave device
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onewire_slave_model #(
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.TS (15 + 0.1)
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) onewire_slave_n_min (
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// configuration
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.ena (slave_ena & (slave_ovd==0)),
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.ovd (slave_ovd ),
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.dat_r (slave_dat_r ),
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.dat_w (slave_dat_w[1]),
|
|
// 1-wire signal
|
|
.owr (owr[1])
|
|
);
|
|
|
|
onewire_slave_model #(
|
|
.TS (60 - 0.1)
|
|
) onewire_slave_n_max (
|
|
// configuration
|
|
.ena (slave_ena & (slave_ovd==0)),
|
|
.ovd (slave_ovd ),
|
|
.dat_r (slave_dat_r ),
|
|
.dat_w (slave_dat_w[2]),
|
|
// 1-wire signal
|
|
.owr (owr[2])
|
|
);
|
|
|
|
// Verilog onewire slave models for overdrive mode
|
|
|
|
// typical slave device
|
|
onewire_slave_model #(
|
|
.TS (30)
|
|
) onewire_slave_o_typ (
|
|
// configuration
|
|
.ena (slave_ena & (slave_ovd==1)),
|
|
.ovd (slave_ovd ),
|
|
.dat_r (slave_dat_r ),
|
|
.dat_w (slave_dat_w[0]),
|
|
// 1-wire signal
|
|
.owr (owr[0])
|
|
);
|
|
|
|
// fast slave device
|
|
onewire_slave_model #(
|
|
.TS (16)
|
|
) onewire_slave_o_min (
|
|
// configuration
|
|
.ena (slave_ena & (slave_ovd==1)),
|
|
.ovd (slave_ovd ),
|
|
.dat_r (slave_dat_r ),
|
|
.dat_w (slave_dat_w[1]),
|
|
// 1-wire signal
|
|
.owr (owr[1])
|
|
);
|
|
|
|
onewire_slave_model #(
|
|
.TS (47)
|
|
) onewire_slave_o_max (
|
|
// configuration
|
|
.ena (slave_ena & (slave_ovd==1)),
|
|
.ovd (slave_ovd ),
|
|
.dat_r (slave_dat_r ),
|
|
.dat_w (slave_dat_w[2]),
|
|
// 1-wire signal
|
|
.owr (owr[2])
|
|
);
|
|
|
|
`endif
|
|
|
|
endmodule
|
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No newline at end of file
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