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# sockit_owm
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###############################################################################
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# Iztok Jeras 2010.06.13.18:29:39
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# #
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# 1-wire (onewire) master
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# Minimalistic 1-wire (onewire) master with Avalon MM bus interface #
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# #
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# Copyright (C) 2010 Iztok Jeras #
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# #
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###############################################################################
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# #
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# This script is free hardware: you can redistribute it and/or modify #
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# it under the terms of the GNU Lesser General Public License #
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# as published by the Free Software Foundation, either #
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# version 3 of the License, or (at your option) any later version. #
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# #
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# This RTL is distributed in the hope that it will be useful, #
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# but WITHOUT ANY WARRANTY; without even the implied warranty of #
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the #
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# GNU General Public License for more details. #
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# #
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# You should have received a copy of the GNU General Public License #
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# along with this program. If not, see <http:#www.gnu.org/licenses/>. #
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# #
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###############################################################################
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# request TCL package from ACDS 9.1
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# request TCL package from Altera tools version 10.0
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package require -exact sopc 9.1
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package require -exact sopc 10.0
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# module sockit_owm
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# module sockit_owm
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set_module_property DESCRIPTION "1-wire (onewire) master"
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set_module_property NAME sockit_owm
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set_module_property NAME sockit_owm
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set_module_property VERSION 1.1
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set_module_property VERSION 1.3
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set_module_property INTERNAL false
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set_module_property GROUP "Interface Protocols/Serial"
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set_module_property GROUP "Interface Protocols/Serial"
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set_module_property DISPLAY_NAME "1-wire (onewire) master"
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set_module_property DESCRIPTION "1-wire (onewire) master"
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set_module_property AUTHOR "Iztok Jeras"
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set_module_property AUTHOR "Iztok Jeras"
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set_module_property DISPLAY_NAME "1-wire (onewire)"
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set_module_property TOP_LEVEL_HDL_FILE sockit_owm.v
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set_module_property TOP_LEVEL_HDL_FILE sockit_owm.v
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set_module_property TOP_LEVEL_HDL_MODULE sockit_owm
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set_module_property TOP_LEVEL_HDL_MODULE sockit_owm
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL TRUE
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# callbacks
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set_module_property VALIDATION_CALLBACK validation_callback
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set_module_property VALIDATION_CALLBACK validation_callback
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set_module_property ELABORATION_CALLBACK elaboration_callback
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set_module_property ELABORATION_CALLBACK elaboration_callback
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# TODO add_documentation_link
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# documentation links and files
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add_documentation_link WEBLINK https://github.com/jeras/sockit_owm
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add_documentation_link WEBLINK http://opencores.org/project,sockit_owm
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add_documentation_link DATASHEET doc/sockit_owm.pdf
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# RTL files
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# RTL files
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add_file sockit_owm.v {SYNTHESIS SIMULATION}
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add_file hdl/sockit_owm.v {SYNTHESIS SIMULATION}
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# parameters
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# parameters
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add_parameter OVD_E BOOLEAN
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set_parameter_property OVD_E DESCRIPTION "Implementation of overdrive enable, disabling it can spare a small amount of logic."
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set_parameter_property OVD_E DEFAULT_VALUE 1
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set_parameter_property OVD_E UNITS None
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set_parameter_property OVD_E AFFECTS_GENERATION false
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set_parameter_property OVD_E HDL_PARAMETER true
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add_parameter CDR_E BOOLEAN
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set_parameter_property CDR_E DESCRIPTION "Implementation of clock divider ratio registers, disabling it can spare a small amount of logic."
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set_parameter_property CDR_E DEFAULT_VALUE 0
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set_parameter_property CDR_E UNITS None
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set_parameter_property CDR_E AFFECTS_GENERATION false
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set_parameter_property CDR_E HDL_PARAMETER true
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add_parameter BDW INTEGER
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add_parameter BDW INTEGER
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set_parameter_property BDW DESCRIPTION "CPU interface data bus width"
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set_parameter_property BDW DESCRIPTION "CPU interface data bus width"
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#set_parameter_property BDW DISPLAY_NAME BDW
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set_parameter_property BDW VISIBLE false
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set_parameter_property BDW DISPLAY_HINT "radio"
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set_parameter_property BDW DEFAULT_VALUE 32
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set_parameter_property BDW DEFAULT_VALUE 32
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set_parameter_property BDW ALLOWED_RANGES {8 32}
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set_parameter_property BDW ALLOWED_RANGES {8 32}
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set_parameter_property BDW UNITS bits
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set_parameter_property BDW UNITS bits
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set_parameter_property BDW ENABLED false
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set_parameter_property BDW ENABLED false
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set_parameter_property BDW AFFECTS_GENERATION false
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set_parameter_property BDW AFFECTS_GENERATION false
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set_parameter_property BDW HDL_PARAMETER true
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set_parameter_property BDW HDL_PARAMETER true
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add_parameter OVD_E BOOLEAN
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add_parameter BAW INTEGER
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set_parameter_property OVD_E DESCRIPTION "Implementation of overdrive enable, disabling it can spare a small amount of logic."
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set_parameter_property BAW DESCRIPTION "CPU interface address bus width"
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#set_parameter_property OVD_E DISPLAY_NAME OVD_E
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set_parameter_property BAW VISIBLE false
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set_parameter_property OVD_E DEFAULT_VALUE 1
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set_parameter_property BAW DEFAULT_VALUE 1
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set_parameter_property OVD_E UNITS None
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set_parameter_property BAW ALLOWED_RANGES {1 2}
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set_parameter_property OVD_E AFFECTS_GENERATION false
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set_parameter_property BAW UNITS bits
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set_parameter_property OVD_E HDL_PARAMETER true
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set_parameter_property BAW ENABLED false
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set_parameter_property BAW AFFECTS_GENERATION false
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set_parameter_property BAW HDL_PARAMETER true
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add_parameter OWN INTEGER
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add_parameter OWN INTEGER
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set_parameter_property OWN DESCRIPTION "Nummber of 1-wire channels"
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set_parameter_property OWN DESCRIPTION "Nummber of 1-wire channels"
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#set_parameter_property OWN DISPLAY_NAME OWN
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#set_parameter_property OWN DISPLAY_NAME OWN
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#set_parameter_property BTP_N DISPLAY_HINT "drop-down"
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set_parameter_property OWN DEFAULT_VALUE 1
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set_parameter_property OWN DEFAULT_VALUE 1
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set_parameter_property OWN ALLOWED_RANGES {1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16}
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set_parameter_property OWN ALLOWED_RANGES {1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16}
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set_parameter_property OWN AFFECTS_GENERATION false
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set_parameter_property OWN AFFECTS_GENERATION false
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set_parameter_property OWN AFFECTS_ELABORATION true
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set_parameter_property OWN AFFECTS_ELABORATION true
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set_parameter_property OWN HDL_PARAMETER true
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set_parameter_property OWN HDL_PARAMETER true
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set_parameter_property F_CLK SYSTEM_INFO {CLOCK_RATE clock_reset}
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set_parameter_property F_CLK SYSTEM_INFO {CLOCK_RATE clock_reset}
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set_parameter_property F_CLK DISPLAY_NAME F_CLK
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set_parameter_property F_CLK DISPLAY_NAME F_CLK
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set_parameter_property F_CLK DESCRIPTION "System clock frequency"
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set_parameter_property F_CLK DESCRIPTION "System clock frequency"
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set_parameter_property F_CLK UNITS megahertz
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set_parameter_property F_CLK UNITS megahertz
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add_parameter CDR_N POSITIVE
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add_parameter CDR_N NATURAL
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set_parameter_property CDR_N DERIVED true
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set_parameter_property CDR_N DERIVED true
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set_parameter_property CDR_N DESCRIPTION "Clock divider ratio for normal mode"
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set_parameter_property CDR_N DESCRIPTION "Clock divider ratio for normal mode"
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set_parameter_property CDR_N DISPLAY_NAME CDR_N
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set_parameter_property CDR_N DISPLAY_NAME CDR_N
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set_parameter_property CDR_N DEFAULT_VALUE 5
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set_parameter_property CDR_N DEFAULT_VALUE 5
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set_parameter_property CDR_N AFFECTS_GENERATION false
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set_parameter_property CDR_N AFFECTS_GENERATION false
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set_parameter_property CDR_N HDL_PARAMETER true
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set_parameter_property CDR_N HDL_PARAMETER true
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add_parameter CDR_O POSITIVE
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add_parameter CDR_O NATURAL
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set_parameter_property CDR_O DERIVED true
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set_parameter_property CDR_O DERIVED true
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set_parameter_property CDR_O DESCRIPTION "Clock divider ratio for overdrive mode"
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set_parameter_property CDR_O DESCRIPTION "Clock divider ratio for overdrive mode"
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set_parameter_property CDR_O DISPLAY_NAME CDR_O
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set_parameter_property CDR_O DISPLAY_NAME CDR_O
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set_parameter_property CDR_O DEFAULT_VALUE 1
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set_parameter_property CDR_O DEFAULT_VALUE 1
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set_parameter_property CDR_O AFFECTS_GENERATION false
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set_parameter_property CDR_O AFFECTS_GENERATION false
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set_interface_property s1 writeWaitTime 0
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set_interface_property s1 writeWaitTime 0
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set_interface_property s1 ASSOCIATED_CLOCK clock_reset
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set_interface_property s1 ASSOCIATED_CLOCK clock_reset
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set_interface_property s1 ENABLED true
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set_interface_property s1 ENABLED true
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add_interface_port s1 bus_read read Input 1
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add_interface_port s1 bus_ren read Input 1
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add_interface_port s1 bus_write write Input 1
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add_interface_port s1 bus_wen write Input 1
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add_interface_port s1 bus_writedata writedata Input BDW
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add_interface_port s1 bus_adr address Input BAW
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add_interface_port s1 bus_readdata readdata Output BDW
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add_interface_port s1 bus_wdt writedata Input BDW
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add_interface_port s1 bus_rdt readdata Output BDW
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# connection point irq
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# connection point irq
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add_interface irq interrupt end
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add_interface irq interrupt end
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set_interface_property irq associatedClock clock_reset
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set_interface_property irq associatedClock clock_reset
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set_interface_property irq associatedAddressablePoint s1
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set_interface_property irq associatedAddressablePoint s1
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set_interface_property irq ASSOCIATED_CLOCK clock_reset
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set_interface_property irq ASSOCIATED_CLOCK clock_reset
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set_interface_property irq ENABLED true
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set_interface_property irq ENABLED true
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add_interface_port irq bus_interrupt irq Output 1
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add_interface_port irq bus_irq irq Output 1
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# connection point conduit
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# connection point conduit
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add_interface ext conduit end
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add_interface ext conduit end
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set_interface_property ext ENABLED true
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set_interface_property ext ENABLED true
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add_interface_port ext onewire_p export Output 1
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add_interface_port ext owr_p export Output OWN
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add_interface_port ext onewire_e export Output 1
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add_interface_port ext owr_e export Output OWN
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add_interface_port ext onewire_i export Input 1
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add_interface_port ext owr_i export Input OWN
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proc validation_callback {} {
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proc validation_callback {} {
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# check if overdrive is enabled
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# check if overdrive is enabled
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set ovd [get_parameter_value OVD_E]
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set ovd_e [get_parameter_value OVD_E]
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# get clock frequency in Hz
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# get clock frequency in Hz
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set f [get_parameter_value F_CLK]
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set f [get_parameter_value F_CLK]
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# get base time periods
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# get base time periods
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set btp_n [get_parameter_value BTP_N]
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set btp_n [get_parameter_value BTP_N]
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set btp_o [get_parameter_value BTP_O]
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set btp_o [get_parameter_value BTP_O]
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# disable editing od dividers
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# enable/disable editing of overdrive divider
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set_parameter_property BTP_O ENABLED [expr {$ovd ? "true" : "false"}]
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set_parameter_property BTP_O ENABLED [expr {$ovd_e ? "true" : "false"}]
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# compute normal mode divider
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# compute normal mode divider
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if {$btp_n=="5.0"} {
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if {$btp_n=="5.0"} {
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set d_n [expr {$f/200000}]
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set d_n [expr {$f/200000}]
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set t_n [expr {1000000.0/($f/$d_n)}]
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set t_n [expr {1000000.0/($f/$d_n)}]
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set e_n [expr {$t_n/5.0-1}]
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set e_n [expr {$t_n/5.0-1}]
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set d_n [expr {$f/133333}]
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set d_n [expr {$f/133333}]
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set t_n [expr {1000000.0/($f/$d_n)}]
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set t_n [expr {1000000.0/($f/$d_n)}]
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set e_n [expr {$t_n/7.5-1}]
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set e_n [expr {$t_n/7.5-1}]
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} elseif {$btp_n=="6.0"} {
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} elseif {$btp_n=="6.0"} {
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set d_n [expr {$f/133333}]
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set d_n [expr {$f/133333}]
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set t_n [expr {1000000.0/($f/$d_n)}]
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set t_n [expr {$d_n*1000000.0/$f}]
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if {(6.0<=$t_n) && ($t_n<=7.5)} {
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if {$t_n>7.5} {
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set e_n 0.0
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set e_n [expr {$t_n/7.5-1}]
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} else {
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} elseif {6.0>$t_n} {
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set e_n [expr {$t_n/6.0-1}]
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set e_n [expr {$t_n/6.0-1}]
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} else {
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set e_n 0.0
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}
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}
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}
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}
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# compute overdrive mode divider
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# compute overdrive mode divider
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if {$btp_o=="1.0"} {
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if {$btp_o=="1.0"} {
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set d_o [expr {$f/1000000}]
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set d_o [expr {$f/1000000}]
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set t_o [expr {1000000.0/($f/$d_o)}]
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set t_o [expr {1000000.0/($f/$d_o)}]
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set e_o [expr {$t_o/1.0-1}]
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set e_o [expr {$t_o/1.0-1}]
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} elseif {$btp_o=="0.5"} {
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} elseif {$btp_o=="0.5"} {
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set d_o [expr {$f/1500000}]
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set d_o [expr {$f/1500000}]
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set t_o [expr {1000000.0/($f/$d_o)}]
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set t_o [expr {$d_o*1000000.0/$f}]
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if {(0.5<=$t_o) && ($t_o<=(2.0/3))} {
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if {$t_o>(2.0/3)} {
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set e_o 0.0
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set e_o [expr {$t_o/(2.0/3)-1}]
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} else {
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} elseif {0.5>$t_o} {
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set e_o [expr {$t_o/0.5-1}]
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set e_o [expr {$t_o/0.5-1}]
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} else {
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set e_o 0.0
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}
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}
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}
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}
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# set divider values
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# set divider values
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set_parameter_value CDR_N $d_n
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set_parameter_value CDR_N [expr {$d_n-1}]
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if {$ovd} {set_parameter_value CDR_O $d_o}
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if {$ovd_e} {set_parameter_value CDR_O [expr {$d_o-1}]}
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# report BTP values and relative errors
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# report BTP values and relative errors
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send_message info "BTP_N (normal mode 'base time period') is [format %.2f $t_n], relative error is [format %.1f [expr {$e_n*100}]]%."
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send_message info "BTP_N (normal mode 'base time period') is [format %.2f $t_n], relative error is [format %.1f [expr {$e_n*100}]]%."
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send_message info "BTP_O (overdrive mode 'base time period') is [format %.2f $t_o], relative error is [format %.1f [expr {$e_o*100}]]%."
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send_message info "BTP_O (overdrive mode 'base time period') is [format %.2f $t_o], relative error is [format %.1f [expr {$e_o*100}]]%."
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# repport validatio errors if relative error are outside accepted bounds (2%)
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# repport validatio errors if relative error are outside accepted bounds (2%)
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if {abs($e_n)>0.02} {send_message error "BTP_N is outside accepted bounds (relative error > 2%). Use a different 'base time period' or system frequency."}
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if {abs($e_n)>0.02} {send_message error "BTP_N is outside accepted bounds (relative error > 2%). Use a different 'base time period' or system frequency."}
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}
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}
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proc elaboration_callback {} {
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proc elaboration_callback {} {
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# add software defines
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# add software defines
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set_module_assignment embeddedsw.CMacro.OWN [get_parameter_value OWN ]
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set_module_assignment embeddedsw.CMacro.OWN [get_parameter_value OWN ]
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set_module_assignment embeddedsw.CMacro.CDR_E [expr {[get_parameter_value CDR_E]?1:0}]
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set_module_assignment embeddedsw.CMacro.OVD_E [expr {[get_parameter_value OVD_E]?1:0}]
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set_module_assignment embeddedsw.CMacro.OVD_E [expr {[get_parameter_value OVD_E]?1:0}]
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set_module_assignment embeddedsw.CMacro.BTP_N [get_parameter_value BTP_N]
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set_module_assignment embeddedsw.CMacro.BTP_O [get_parameter_value BTP_O]
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}
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set_module_assignment embeddedsw.CMacro.BTP_N \"[get_parameter_value BTP_N]\"
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set_module_assignment embeddedsw.CMacro.BTP_O \"[get_parameter_value BTP_O]\"
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set_module_assignment embeddedsw.CMacro.CDR_N [get_parameter_value CDR_N]
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set_module_assignment embeddedsw.CMacro.CDR_O [get_parameter_value CDR_O]
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# get clock frequency in Hz
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set f [get_parameter_value F_CLK]
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# get base time period
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set btp_n [get_parameter_value BTP_N]
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# get clock divider ratio
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set cdr_n [get_parameter_value CDR_N]
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# compute delay time in seconds [s]
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if {$btp_n=="5.0"} {
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set t_dly [expr {200.*($cdr_n+1)/$f}]
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} elseif {$btp_n=="7.5"} {
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set t_dly [expr {128.*($cdr_n+1)/$f}]
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} elseif {$btp_n=="6.0"} {
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set t_dly [expr {160.*($cdr_n+1)/$f}]
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}
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# give the software a u16.16 representation of delay frequency in kilo hertz [kHz]
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set_module_assignment embeddedsw.CMacro.F_DLY [format %.0f [expr {pow(2,16) / (1000*$t_dly)}]]
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}
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