| Line 45... |
Line 45... |
output rx_got_null,
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output rx_got_null,
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output rx_got_nchar,
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output rx_got_nchar,
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output rx_got_time_code,
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output rx_got_time_code,
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output rx_got_fct,
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output rx_got_fct,
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output [8:0] rx_data_flag,
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output reg [8:0] rx_data_flag,
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output rx_buffer_write,
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output reg rx_buffer_write,
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output [7:0] rx_time_out,
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output reg [7:0] rx_time_out,
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output rx_tick_out
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output reg rx_tick_out
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);
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);
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reg [4:0] counter_neg;
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reg [4:0] counter_neg;
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| Line 95... |
Line 95... |
reg [9:0] data_l_r;
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reg [9:0] data_l_r;
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reg parity_error;
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reg parity_error;
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wire check_c_d;
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wire check_c_d;
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reg rx_data_take;
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//CLOCK RECOVERY
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//CLOCK RECOVERY
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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| Line 111... |
Line 113... |
assign rx_error = parity_error;
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assign rx_error = parity_error;
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assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
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assign rx_buffer_write = ( (control[2:0] == 3'd5 & is_control) == 1'b1 | (control[2:0] != 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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assign rx_data_flag = ( (control[2:0] == 3'd6 & is_control) == 1'b1 )?9'b100000001:
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( (control[2:0] == 3'd5 & is_control) == 1'b1 )?9'b100000000:
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( (control[2:0] != 3'd7 & is_data) == 1'b1)?data[8:0]:9'd0;
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assign rx_time_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?timecode[7:0]:8'd0;
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assign rx_tick_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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| Line 293... |
Line 287... |
control <= 4'd0;
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control <= 4'd0;
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control_l_r <= 4'd0;
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control_l_r <= 4'd0;
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data <= 10'd0;
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data <= 10'd0;
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data_l_r <= 10'd0;
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data_l_r <= 10'd0;
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rx_data_flag <= 9'd0;
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rx_buffer_write <= 1'b0;
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rx_data_take <= 1'b0;
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timecode <= 10'd0;
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timecode <= 10'd0;
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rx_time_out <= 8'd0;
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rx_tick_out <= 1'b0;
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last_is_control <=1'b0;
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last_is_control <=1'b0;
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last_is_data <=1'b0;
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last_is_data <=1'b0;
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last_is_timec <=1'b0;
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last_is_timec <=1'b0;
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| Line 307... |
Line 306... |
last_was_timec <=1'b0;
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last_was_timec <=1'b0;
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end
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end
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else
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else
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begin
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begin
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rx_buffer_write <= rx_data_take;
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rx_data_flag <= data[8:0];
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rx_time_out <= timecode;
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if((control[2:0] != 3'd7 & is_data) == 1'b1)
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if((control[2:0] != 3'd7 & is_data) == 1'b1)
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begin
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begin
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data <= {bit_d_9,bit_d_8,bit_d_7,bit_d_6,bit_d_5,bit_d_4,bit_d_3,bit_d_2,bit_d_1,bit_d_0};
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data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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data_l_r <= data;
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data_l_r <= data;
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rx_data_take <= 1'b1;
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rx_tick_out <= 1'b0;
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last_is_control <=1'b0;
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last_is_control <=1'b0;
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last_is_data <=1'b1;
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last_is_data <=1'b1;
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last_is_timec <=1'b0;
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last_is_timec <=1'b0;
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last_was_control <= last_is_control;
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last_was_control <= last_is_control;
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last_was_data <= last_is_data ;
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last_was_data <= last_is_data ;
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| Line 324... |
Line 332... |
end
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end
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else if((control[2:0] == 3'd7 & is_data) == 1'b1)
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else if((control[2:0] == 3'd7 & is_data) == 1'b1)
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begin
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begin
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timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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rx_tick_out <= 1'b1;
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rx_data_take <= 1'b0;
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last_is_control <= 1'b0;
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last_is_control <= 1'b0;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b1;
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last_is_timec <= 1'b1;
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last_was_control <= last_is_control;
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last_was_control <= last_is_control;
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| Line 338... |
Line 348... |
begin
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begin
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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control_l_r <= control[3:0];
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control_l_r <= control[3:0];
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/*
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if((control[2:0] == 3'd6 & is_control) == 1'b1 )
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if(last_is_data & last_was_data)
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begin
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begin
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data <= 10'b0100000001;
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data <= 10'd0;
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rx_data_take <= 1'b1;
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data_l_r <= 10'd0;
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end
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timecode <= 10'd0;
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else if( (control[2:0] == 3'd5 & is_control) == 1'b1 )
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end
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begin
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*/
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data <= 10'b0100000000;
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rx_data_take <= 1'b1;
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end
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else
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begin
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rx_data_take <= 1'b0;
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end
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rx_tick_out <= 1'b0;
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last_is_control <= 1'b1;
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last_is_control <= 1'b1;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b0;
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last_is_timec <= 1'b0;
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last_was_control <= last_is_control;
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last_was_control <= last_is_control;
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last_was_data <= last_is_data ;
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last_was_data <= last_is_data ;
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