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-- In order to preserve global clocking resources, the core clocking scheme is completely based
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-- In order to preserve global clocking resources, the core clocking scheme is completely based
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-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
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-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
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-- the spi clock generator and the input sampling clock.
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-- the spi clock generator and the input sampling clock.
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-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock
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-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock
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-- for the core clocking.
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-- for the core clocking.
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-- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only
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-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
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-- differential interconnect delay skew.
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-- differential interconnect delay skew.
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-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
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-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
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-- enables are used to control clocking of all internal synchronous circuitry.
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-- enables are used to control clocking of all internal synchronous circuitry.
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-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
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-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
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-- based on the configuration of CPOL and CPHA.
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-- based on the configuration of CPOL and CPHA.
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