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Release 13.1 par O.40d (nt)
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Release 13.1 par O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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DEVELOP-W7:: Wed Aug 10 22:56:51 2011
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DEVELOP-W7:: Mon Aug 29 00:08:38 2011
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par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
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par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
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spi_master_atlys_top.ncd spi_master_atlys_top.pcf
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spi_master_atlys_top.ncd spi_master_atlys_top.pcf
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Line 25... |
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Device Utilization Summary:
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Device Utilization Summary:
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 209 out of 54,576 1%
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Number of Slice Registers: 224 out of 54,576 1%
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Number used as Flip Flops: 209
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Number used as Flip Flops: 224
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Number used as Latches: 0
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 145 out of 27,288 1%
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Number of Slice LUTs: 177 out of 27,288 1%
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Number used as logic: 127 out of 27,288 1%
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Number used as logic: 167 out of 27,288 1%
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Number using O6 output only: 75
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Number using O6 output only: 112
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Number using O5 output only: 13
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Number using O5 output only: 28
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Number using O5 and O6: 39
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Number using O5 and O6: 27
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Number used as ROM: 0
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Number used as ROM: 0
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Number used as Memory: 4 out of 6,408 1%
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Number used as Memory: 4 out of 6,408 1%
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Number used as Dual Port RAM: 0
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Number used as Dual Port RAM: 0
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Number used as Single Port RAM: 0
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Number used as Single Port RAM: 0
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Number used as Shift Register: 4
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Number used as Shift Register: 4
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Number using O6 output only: 4
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Number using O6 output only: 4
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Number using O5 output only: 0
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Number using O5 output only: 0
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Number using O5 and O6: 0
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Number using O5 and O6: 0
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Number used exclusively as route-thrus: 14
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Number used exclusively as route-thrus: 6
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Number with same-slice register load: 12
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Number with same-slice register load: 4
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Number with same-slice carry load: 2
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Number with same-slice carry load: 2
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Number with other load: 0
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Number with other load: 0
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of occupied Slices: 91 out of 6,822 1%
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Number of occupied Slices: 102 out of 6,822 1%
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Number of LUT Flip Flop pairs used: 225
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Number of LUT Flip Flop pairs used: 272
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Number with an unused Flip Flop: 49 out of 225 21%
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Number with an unused Flip Flop: 64 out of 272 23%
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Number with an unused LUT: 80 out of 225 35%
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Number with an unused LUT: 95 out of 272 34%
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Number of fully used LUT-FF pairs: 96 out of 225 42%
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Number of fully used LUT-FF pairs: 113 out of 272 41%
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Number of slice register sites lost
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Number of slice register sites lost
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to control set restrictions: 0 out of 54,576 0%
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to control set restrictions: 0 out of 54,576 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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one Flip Flop within a slice. A control set is a unique combination of
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The Slice Logic Distribution report is not meaningful if the design is
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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IO Utilization:
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Number of bonded IOBs: 63 out of 218 28%
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Number of bonded IOBs: 63 out of 218 28%
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Number of LOCed IOBs: 43 out of 63 68%
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Number of LOCed IOBs: 47 out of 63 74%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Finished initial Timing Analysis. REAL time: 4 secs
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Finished initial Timing Analysis. REAL time: 4 secs
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Starting Router
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Starting Router
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Phase 1 : 910 unrouted; REAL time: 5 secs
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Phase 1 : 1133 unrouted; REAL time: 5 secs
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Phase 2 : 760 unrouted; REAL time: 6 secs
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Phase 2 : 972 unrouted; REAL time: 6 secs
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Phase 3 : 207 unrouted; REAL time: 7 secs
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Phase 3 : 282 unrouted; REAL time: 7 secs
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Phase 4 : 207 unrouted; (Par is working to improve performance) REAL time: 9 secs
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Phase 4 : 282 unrouted; (Par is working to improve performance) REAL time: 9 secs
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Updating file: spi_master_atlys_top.ncd with current fully routed design.
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Updating file: spi_master_atlys_top.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net gcl | SETUP | N/A| 5.299ns| N/A| 0
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Autotimespec constraint for clock net gcl | SETUP | N/A| 4.888ns| N/A| 0
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k_i_BUFGP | HOLD | 0.388ns| | 0| 0
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k_i_BUFGP | HOLD | 0.378ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net Ins | SETUP | N/A| 5.052ns| N/A| 0
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Autotimespec constraint for clock net Ins | SETUP | N/A| 3.948ns| N/A| 0
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t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.497ns| | 0| 0
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t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.459ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 10 secs
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Total REAL time to PAR completion: 10 secs
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Total CPU time to PAR completion: 10 secs
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Total CPU time to PAR completion: 10 secs
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Peak Memory Usage: 269 MB
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Peak Memory Usage: 264 MB
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Placer: Placement generated during map.
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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