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Line 15... |
*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module sound1942;
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module sound1942;
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wire [7:0]cpu_in, cpu_out;
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wire [15:0]adr;
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wire m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n;
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wire bus_error;
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// inputs to Z80
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// inputs to Z80
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reg reset_n, clk, wait_n, int_n, nmi_n, busrq_n, sound_clk;
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reg reset_n, clk, int_n, sound_clk;
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initial begin
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initial begin
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//$dumpfile("dump.lxt");
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//$dumpfile("dump.lxt");
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//$dumpvars(1,map.ym2203_0);
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//$dumpvars(1,map.ym2203_0);
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// $dumpvars();
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// $dumpvars();
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// $dumpon;
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// $dumpon;
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// $shm_open("1942.shm");
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// $shm_open("1942.shm");
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// $shm_probe( sound1942, "ACTFS" );
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// $shm_probe( sound1942, "ACTFS" );
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reset_n=0;
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reset_n=0;
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nmi_n=1;
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wait_n=1;
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#1500 reset_n=1;
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#1500 reset_n=1;
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// change finish time depending on song
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// change finish time depending on song
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// #400e6 $finish;
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//#4e6 $finish;
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#10e9 $finish;
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#5e9 $finish;
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end
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end
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always begin // main clock
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always begin // main clock
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clk=0;
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clk=0;
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forever clk = #167 ~clk;
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forever clk = #167 ~clk;
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| Line 59... |
Line 53... |
//$display("IRQ request @ %t us",$time/1e6);
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//$display("IRQ request @ %t us",$time/1e6);
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#(int_low_time) int_n=1;
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#(int_low_time) int_n=1;
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end
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end
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end
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end
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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tv80n cpu( //outputs
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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.m1_n(m1_n), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n),
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computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
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.rfsh_n(rfsh_n), .halt_n(halt_n), .busak_n(busak_n), .A(adr), .do(cpu_out),
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.int_n(int_n), .reset_n(reset_n),
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// Inputs
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.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
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.reset_n(reset_n), .clk(clk), .wait_n(wait_n),
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.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
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.int_n(int_n), .nmi_n(nmi_n), .busrq_n(busrq_n), .di(cpu_in) );
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// sound amplifier:
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wire [15:0] amp0_y, amp1_y;
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MAP map( .adr(adr), .din(cpu_out), .dout(cpu_in), .clk(clk),
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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.sound_clk( sound_clk ), .wr_n(wr_n), .rd_n(rd_n),
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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.bus_error(bus_error), .reset_n(reset_n) );
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endmodule
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endmodule
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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module MAP(
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module computer_1942
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input [15:0] adr,
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#(parameter dump_regs=0) // set to 1 to dump sqmusic registers
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input [7:0] din,
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(
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output [7:0] dout,
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input clk,
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input clk,
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input sound_clk,
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input sound_clk,
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input rd_n,
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input wr_n,
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input reset_n,
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input reset_n,
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output bus_error );
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input int_n,
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output [3:0] ay0_a,
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output [3:0] ay0_b,
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output [3:0] ay0_c,
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output [3:0] ay1_a,
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output [3:0] ay1_b,
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output [3:0] ay1_c
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);
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reg wait_n, nmi_n, busrq_n;
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wire [7:0]cpu_in, cpu_out;
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wire [15:0]adr;
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wire m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n;
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wire bus_error;
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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wire [15:0] amp0_y, amp1_y;
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wire [15:0] amp0_y, amp1_y;
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wire [7:0]ram_out, rom_out, latch_out;
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wire [7:0]ram_out, rom_out, latch_out;
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| Line 98... |
Line 100... |
wire latch_enable = adr==16'h6000 ? 1 : 0;
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wire latch_enable = adr==16'h6000 ? 1 : 0;
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wire ay_0_enable = adr==16'h8000 || adr==16'h8001 ? 1:0;
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wire ay_0_enable = adr==16'h8000 || adr==16'h8001 ? 1:0;
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wire ay_1_enable = adr==16'hC000 || adr==16'hC001 ? 1:0;
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wire ay_1_enable = adr==16'hC000 || adr==16'hC001 ? 1:0;
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assign bus_error = ~ram_enable & ~rom_enable & ~latch_enable &
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assign bus_error = ~ram_enable & ~rom_enable & ~latch_enable &
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~ay_0_enable & ~ay_1_enable;
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~ay_0_enable & ~ay_1_enable;
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assign dout=ram_out | rom_out | latch_out;
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assign cpu_in=ram_out | rom_out | latch_out;
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/*
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/*
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always @(negedge rd_n)
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always @(negedge rd_n)
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if( !rd_n && adr==8'h38 )
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if( !rd_n && adr==8'h38 )
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$display("IRQ processing started @ %t us",$time/1e6);
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$display("IRQ processing started @ %t us",$time/1e6);
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*/
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*/
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RAM ram(.adr(adr[10:0]), .din(din), .dout(ram_out), .enable( ram_enable ),
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initial begin
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nmi_n=1;
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wait_n=1;
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end
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tv80n cpu( //outputs
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.m1_n(m1_n), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n),
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.rfsh_n(rfsh_n), .halt_n(halt_n), .busak_n(busak_n), .A(adr), .do(cpu_out),
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// Inputs
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.reset_n(reset_n), .clk(clk), .wait_n(wait_n),
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.int_n(int_n), .nmi_n(nmi_n), .busrq_n(busrq_n), .di(cpu_in) );
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RAM ram(.adr(adr[10:0]), .din(cpu_out), .dout(ram_out), .enable( ram_enable ),
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.clk(clk), .wr_n(wr_n), .rd_n(rd_n) );
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.clk(clk), .wr_n(wr_n), .rd_n(rd_n) );
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ROM rom(.adr(adr[13:0]), .data(rom_out), .enable(rom_enable),
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ROM rom(.adr(adr[13:0]), .data(rom_out), .enable(rom_enable),
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.rd_n(rd_n), .clk(clk));
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.rd_n(rd_n), .clk(clk));
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SOUND_LATCH sound_latch( .dout(latch_out), .enable(latch_enable),
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SOUND_LATCH sound_latch( .dout(latch_out), .enable(latch_enable),
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.clk(clk), .rd_n(rd_n) );
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.clk(clk), .rd_n(rd_n) );
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// fake_ay ay_0( .adr(adr[0]), .din(din), .clk(clk), .wr_n(~ay_0_enable|wr_n) );
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// fake_ay ay_0( .adr(adr[0]), .din(din), .clk(clk), .wr_n(~ay_0_enable|wr_n) );
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AY_3_8910_capcom ay_0( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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AY_3_8910_capcom #(dump_regs,0) ay_0( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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.din(din), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_0_enable),
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.din(cpu_out), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_0_enable),
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.A(ay0_a), .B(ay0_b), .C(ay0_c) );
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.A(ay0_a), .B(ay0_b), .C(ay0_c) );
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AY_3_8910_capcom ay_1( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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AY_3_8910_capcom #(dump_regs,1) ay_1( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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.din(din), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_1_enable),
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.din(cpu_out), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_1_enable),
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.A(ay1_a), .B(ay1_b), .C(ay1_c) );
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.A(ay1_a), .B(ay1_b), .C(ay1_c) );
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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// initial $dumpvars(0,ym2203_0);
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endmodule
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endmodule
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//////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////
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// this module is used to check the communication of the
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// this module is used to check the communication of the
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// Z80 with the AY-3-8910
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// Z80 with the AY-3-8910
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