| Line 15... |
Line 15... |
module sq_slot(
|
module sq_slot(
|
input clk,
|
input clk,
|
input reset_n,
|
input reset_n,
|
input [10:0] fnumber,
|
input [10:0] fnumber,
|
input [2:0] block,
|
input [2:0] block,
|
input [3:0] multiple
|
input [3:0] multiple,
|
|
output [12:0] linear
|
);
|
);
|
|
|
wire [9:0]phase;
|
wire [9:0]phase;
|
wire [12:0] sin_log, sin_linear;
|
wire [12:0] sin_log, sin_linear;
|
|
|
| Line 39... |
Line 40... |
|
|
sq_pow pow(
|
sq_pow pow(
|
.clk (clk),
|
.clk (clk),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
.x (sin_log),
|
.x (sin_log),
|
.y (sin_linear) );
|
.y (linear) );
|
|
|
endmodule
|
endmodule
|
|
|
module sq_pg(
|
module sq_pg(
|
input clk,
|
input clk,
|
| Line 95... |
Line 96... |
///////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////
|
// sq_pow => reverse the log2 conversion
|
// sq_pow => reverse the log2 conversion
|
module sq_pow(
|
module sq_pow(
|
input clk,
|
input clk,
|
input reset_n,
|
input reset_n,
|
input [12:0]x,
|
input rd_n, // read enable, active low
|
output [12:0]y // LSB is the sign. 0=positive, 1=negative
|
input [12:0]x, // LSB is the sign. 0=positive, 1=negative
|
|
output reg [12:0]y
|
);
|
);
|
|
|
|
parameter st_input = 3'b000;
|
|
parameter st_lut_read = 3'b001;
|
|
parameter st_shift = 3'b010;
|
|
parameter st_sign = 3'b011;
|
|
parameter st_output = 3'b100;
|
|
|
|
reg [2:0] state;
|
reg [12:0] pow_table[255:0];
|
reg [12:0] pow_table[255:0];
|
|
|
initial begin
|
initial begin
|
$readmemh("../tables/pow_table.hex", pow_table);
|
$readmemh("../tables/pow_table.hex", pow_table);
|
end
|
end
|
reg [7:0]index;
|
reg [7:0]index;
|
reg [2:0]exp;
|
reg [3:0]exp;
|
reg sign;
|
reg sign;
|
|
|
wire [12:0] raw = pow_table[index] >> exp;
|
reg [12:0] raw, shifted, final;
|
assign y = sign ? ~raw+13'b1 : raw; // regular 2's complement
|
|
|
|
always @(posedge clk or negedge reset_n ) begin
|
always @(posedge clk or negedge reset_n ) begin
|
if( !reset_n ) begin
|
if( !reset_n ) begin
|
index <= 8'b0;
|
index <= 8'b0;
|
exp <= 3'b0;
|
exp <= 3'b0;
|
sign <= 1'b0;
|
sign <= 1'b0;
|
|
raw <= 13'b0;
|
|
shifted <= 13'b0;
|
|
y <= 12'b0;
|
|
state <= st_input;
|
end
|
end
|
else begin
|
else begin
|
exp <= x[12:10];
|
case ( state )
|
index <= x[9:1];
|
st_input: begin
|
|
if( !rd_n ) begin
|
|
exp <= x[12:9];
|
|
index <= x[8:1];
|
sign <= x[0];
|
sign <= x[0];
|
|
state <= st_lut_read;
|
|
end
|
|
else state <= st_lut_read;
|
|
end
|
|
st_lut_read: begin
|
|
raw <= pow_table[index];
|
|
state <= st_shift;
|
|
end
|
|
st_shift: begin
|
|
shifted <= raw >> exp;
|
|
state <= st_sign;
|
|
end
|
|
st_sign: begin
|
|
final <= sign ? ~shifted + 1'b1 : shifted;
|
|
state <= st_output;
|
|
end
|
|
st_output: begin
|
|
y <= final;
|
|
state <= st_input;
|
|
end
|
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
always @(posedge clk or negedge reset_n ) begin
|
|
if( !reset_n )
|
|
raw <= 13'b0;
|
|
else
|
|
raw <= pow_table[index];
|
|
end
|
|
|
|
always @(posedge clk or negedge reset_n ) begin
|
|
if( !reset_n )
|
|
shifted <= 13'b0;
|
|
else
|
|
shifted <= raw >> exp;
|
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
