OpenCores
URL https://opencores.org/ocsvn/sqmusic/sqmusic/trunk

Subversion Repositories sqmusic

[/] [sqmusic/] [trunk/] [sqm/] [sq_pg.v] - Diff between revs 19 and 20

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 19 Rev 20
Line 16... Line 16... 
        input  clk,
 
        input  clk,
 
        input  reset_n,
 
        input  reset_n,
 
        input  [10:0] fnumber,
 
        input  [10:0] fnumber,
 
        input  [2:0]  block,
 
        input  [2:0]  block,
 
  input  [3:0]  multiple,
 
  input  [3:0]  multiple,
 
  output [12:0] linear
 
  input  [6:0]  totallvl, // total level
 
 
 
  output [13:0] linear
 
);
 
);
 
 
 
 
 
 
 
reg [7:0]state;
 
 
 
 
 
 
 
parameter st_pg_count  = 8'h01;
 
 
 
parameter st_pow_read  = 8'h04;
 
 
 
 
 
wire [9:0]phase;
 
wire [9:0]phase;
 
wire [12:0] sin_log, sin_linear;
 
wire [13:0] sin_log, sin_linear;
 
 
 
reg  pg_ce_n, pow_rd_n;
 
 
 
 
 
 
 
always @(posedge clk or negedge reset_n ) begin
 
 
 
  if (!reset_n) begin
 
 
 
    state   <= 8'b0;
 
 
 
    pg_ce_n <= 1'b1;
 
 
 
    pow_rd_n<= 1'b1;
 
 
 
  end
 
 
 
  else begin
 
 
 
    if( state == 8'd143 )
 
 
 
      state <= 8'd0;
 
 
 
    else
 
 
 
      state <= state+1;
 
 
 
    pg_ce_n <=  state == st_pg_count ? 1'b0 : 1'b1;
 
 
 
    pow_rd_n<=  state == st_pow_read ? 1'b0 : 1'b1;
 
 
 
  end
 
 
 
end
 
 
 
 
 
sq_pg pg(
 
sq_pg pg(
 
  .clk     (clk),
 
  .clk     (clk),
 
  .reset_n (reset_n),
 
  .reset_n (reset_n),
 
  .fnumber (fnumber),
 
  .fnumber (fnumber),
 
  .block   (block),
 
  .block   (block),
 
  .multiple(multiple),
 
  .multiple(multiple),
 
 
 
  .ce_n    (pg_ce_n),
 
  .phase   (phase) );
 
  .phase   (phase) );
 
 
 
 
 
sq_sin sin(
 
sq_sin sin(
 
  .clk     (clk),
 
  .clk     (clk),
 
  .reset_n (reset_n),
 
  .reset_n (reset_n),
 
  .phase   (phase),
 
  .phase   (phase),
 
 
 
  .gain    (totallvl),
 
  .val     (sin_log) );
 
  .val     (sin_log) );
 
 
 
 
 
sq_pow pow(
 
sq_pow pow(
 
  .clk     (clk),
 
  .clk     (clk),
 
  .reset_n (reset_n),
 
  .reset_n (reset_n),
 
 
 
  .rd_n    (pow_rd_n),
 
  .x       (sin_log),
 
  .x       (sin_log),
 
  .y       (linear) );
 
  .y       (linear) );
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
///////////////////////////////////////////////////////////////////
 
module sq_pg(
 
module sq_pg(
 
        input clk,
 
        input clk,
 
        input reset_n,
 
        input reset_n,
 
        input [10:0] fnumber,
 
        input [10:0] fnumber,
 
        input [2:0] block,
 
        input [2:0] block,
 
  input [3:0] multiple,
 
  input [3:0] multiple,
 
 
 
  input ce_n, // count enable, active low
 
        output [9:0]phase );
 
        output [9:0]phase );
 
 
 
 
 
reg [19:0] count;
 
reg [19:0] count;
 
assign phase = count[19:10];
 
assign phase = count[19:10];
 
 
 
 
 
wire [19:0]fmult = fnumber << block;
 
wire [19:0]fmult = fnumber << (block-1);
 
 
 
 
 
always @(posedge clk or negedge reset_n ) begin
 
always @(posedge clk or negedge reset_n ) begin
 
        if( !reset_n )
 
        if( !reset_n )
 
                count <= 20'b0;
 
                count <= 20'b0;
 
        else begin
 
        else begin
 
 
 
          if( !ce_n )
 
          count <= count + ( multiple==4'b0 ? fmult>> 1 : fmult*multiple);
 
          count <= count + ( multiple==4'b0 ? fmult>> 1 : fmult*multiple);
 
 
 
        else
 
 
 
          count <= count;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
///////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////
 
module sq_sin(
 
module sq_sin(
 
  input clk,
 
  input clk,
 
  input reset_n,
 
  input reset_n,
 
 
 
  input [6:0]gain, // gain factor in log scale
 
  input [9:0]phase,
 
  input [9:0]phase,
 
  output [12:0] val // LSB is the sign. 0=positive, 1=negative
 
  output [13:0] val // LSB is the sign. 0=positive, 1=negative
 
);
 
);
 
 
 
 
 
reg [12:0] sin_table[1023:0];
 
reg [12:0] sin_table[1023:0];
 
 
 
 
 
initial begin
 
initial begin
 
  $readmemh("../tables/sin_table.hex", sin_table);
 
  $readmemh("../tables/sin_table.hex", sin_table);
 
end
 
end
 
reg [9:0]last_phase;
 
reg [9:0]last_phase;
 
assign val = sin_table[last_phase];
 
assign val = sin_table[last_phase] + { gain, 6'h0 };
 
 
 
 
 
always @(posedge clk or negedge reset_n ) begin
 
always @(posedge clk or negedge reset_n ) begin
 
        if( !reset_n )
 
        if( !reset_n )
 
                last_phase <= 10'b0;
 
                last_phase <= 10'b0;
 
        else begin
 
        else begin
Line 97... Line 129... 
// sq_pow => reverse the log2 conversion
 
// sq_pow => reverse the log2 conversion
 
module sq_pow(
 
module sq_pow(
 
  input clk,
 
  input clk,
 
  input reset_n,
 
  input reset_n,
 
  input rd_n, // read enable, active low
 
  input rd_n, // read enable, active low
 
  input [12:0]x, // LSB is the sign. 0=positive, 1=negative
 
  input [13:0]x, // LSB is the sign. 0=positive, 1=negative
 
  output reg [12:0]y
 
  output reg [13:0]y
 
);
 
);
 
 
 
 
 
parameter st_input    = 3'b000;
 
parameter st_input    = 3'b000;
 
parameter st_lut_read = 3'b001;
 
parameter st_lut_read = 3'b001;
 
parameter st_shift    = 3'b010;
 
parameter st_shift    = 3'b010;
Line 114... Line 146... 
 
 
 
 
initial begin
 
initial begin
 
  $readmemh("../tables/pow_table.hex", pow_table);
 
  $readmemh("../tables/pow_table.hex", pow_table);
 
end
 
end
 
reg [7:0]index;
 
reg [7:0]index;
 
reg [3:0]exp;
 
reg [4:0]exp;
 
reg sign;
 
reg sign;
 
 
 
 
 
reg [12:0] raw, shifted, final;
 
reg [13:0] raw, shifted, final;
 
 
 
 
 
always @(posedge clk or negedge reset_n ) begin
 
always @(posedge clk or negedge reset_n ) begin
 
        if( !reset_n ) begin
 
        if( !reset_n ) begin
 
                index <= 8'b0;
 
                index <= 8'b0;
 
                exp   <= 3'b0;
 
                exp   <= 3'b0;
 
                sign  <= 1'b0;
 
                sign  <= 1'b0;
 
                raw   <= 13'b0;
 
                raw     <= 14'b0;
 
                shifted <= 13'b0;
 
                shifted <= 14'b0;
 
                y     <= 12'b0;
 
                y       <= 14'b0;
 
                state <= st_input;
 
                state <= st_input;
 
        end
 
        end
 
        else begin
 
        else begin
 
          case ( state )
 
          case ( state )
 
            st_input: begin
 
            st_input: begin
 
              if( !rd_n ) begin
 
              if( !rd_n ) begin
 
                exp   <= x[12:9];
 
                exp   <= x[13:9];
 
                index <= x[8:1];
 
                index <= x[8:1];
 
                sign  <= x[0];
 
                sign  <= x[0];
 
                state <= st_lut_read;
 
                state <= st_lut_read;
 
              end
 
              end
 
              else state <= st_lut_read;
 
              else state <= st_input;
 
              end
 
              end
 
           st_lut_read: begin
 
           st_lut_read: begin
 
              raw   <= pow_table[index];
 
              raw   <= pow_table[index];
 
              state <= st_shift;
 
              state <= st_shift;
 
              end
 
              end
Line 156... Line 188... 
              end
 
              end
 
           st_output: begin
 
           st_output: begin
 
              y     <= final;
 
              y     <= final;
 
              state <= st_input;
 
              state <= st_input;
 
              end
 
              end
 
 
 
           default: begin
 
 
 
              state <= st_input;
 
 
 
              end
 
          endcase
 
          endcase
 
        end
 
        end
 
end
 
end
 
 
 
 
 
always @(posedge clk or negedge reset_n ) begin
 
always @(posedge clk or negedge reset_n ) begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.