| Line 28... |
Line 28... |
input wr_n, // write
|
input wr_n, // write
|
input cs_n, // chip select
|
input cs_n, // chip select
|
output [3:0]A,B,C // channel outputs
|
output [3:0]A,B,C // channel outputs
|
);
|
);
|
|
|
reg [7:0] latches[1:0];
|
reg [3:0] adr_latch;
|
reg core_wr;
|
wire sample = ~cs_n & ~wr_n;
|
wire sample = clk & ~cs_n & ~wr_n;
|
wire core_wr = adr & sample;
|
reg count;
|
reg count;
|
|
|
always @(posedge sound_clk or negedge reset_n) begin
|
always @(posedge clk or negedge reset_n) begin
|
if(!reset_n) begin
|
if(!reset_n)
|
count=0;
|
adr_latch <= 0;
|
end
|
else
|
else begin
|
if( sample && adr==0 )
|
if( !count && core_wr) count=1;
|
adr_latch <= din[3:0];
|
else if( core_wr ) begin
|
|
count=0;
|
|
core_wr=0;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge sample or negedge reset_n) begin
|
|
if(!reset_n) begin
|
|
latches[0]=0;
|
|
latches[1]=0;
|
|
end
|
|
else begin
|
|
latches[adr] = din;
|
|
if(adr) core_wr=1;
|
|
end
|
|
end
|
end
|
|
|
SQMUSIC #(dump_writes, id) core( .reset_n(reset_n), .clk(sound_clk), .data_in(latches[1]),
|
SQMUSIC #(dump_writes, id) core( .reset_n(reset_n), .clk(sound_clk), .data_in(din),
|
.adr( latches[0][3:0] ), .rd(1'b0), .wr(core_wr), .A(A), .B(B), .C(C) );
|
.adr( adr_latch ), .rd(1'b0), .wr(core_wr), .A(A), .B(B), .C(C) );
|
endmodule
|
endmodule
|
|
|
|
//////////////////////////////////////////////////////////////////////////////
|
/* The AY core does
|
/* The AY core does
|
*/
|
*/
|
module SQMUSIC
|
module SQMUSIC
|
#( parameter dump_writes=0, parameter id=0 ) // set to 1 to dump register writes
|
#( parameter dump_writes=0, parameter id=0 ) // set to 1 to dump register writes
|
( // note that input ports are not multiplexed
|
( // note that input ports are not multiplexed
|
| Line 108... |
Line 93... |
|
|
assign A=regarray[10][4]? envelope&{4{Amix}} : regarray[10][3:0]&{4{Amix}};
|
assign A=regarray[10][4]? envelope&{4{Amix}} : regarray[10][3:0]&{4{Amix}};
|
assign B=regarray[11][4]? envelope&{4{Bmix}} : regarray[10][3:0]&{4{Bmix}};
|
assign B=regarray[11][4]? envelope&{4{Bmix}} : regarray[10][3:0]&{4{Bmix}};
|
assign C=regarray[12][4]? envelope&{4{Cmix}} : regarray[10][3:0]&{4{Cmix}};
|
assign C=regarray[12][4]? envelope&{4{Cmix}} : regarray[10][3:0]&{4{Cmix}};
|
|
|
integer aux;
|
|
|
|
// 16-count divider
|
// 16-count divider
|
always @(posedge clk or reset_n) begin
|
always @(posedge clk or negedge reset_n) begin
|
if( !reset_n)
|
if( !reset_n)
|
clkdiv16=0;
|
clkdiv16<=0;
|
else
|
else
|
clkdiv16<=clkdiv16+1;
|
clkdiv16<=clkdiv16+1;
|
end
|
end
|
|
|
always @(posedge clk or reset_n) begin
|
integer aux;
|
|
always @(posedge clk or negedge reset_n) begin
|
if( !reset_n ) begin
|
if( !reset_n ) begin
|
data_out=0;
|
data_out=0;
|
for(aux=0;aux<=15;aux=aux+1) regarray[aux]=0;
|
for(aux=0;aux<=15;aux=aux+1) regarray[aux]=0;
|
end
|
end
|
else begin
|
else begin
|
| Line 157... |
Line 141... |
|
|
initial clkdiv=0;
|
initial clkdiv=0;
|
|
|
assign div = period==1 ? clk : clkdiv;
|
assign div = period==1 ? clk : clkdiv;
|
|
|
always @(posedge clk or reset_n) begin
|
always @(posedge clk or negedge reset_n) begin
|
if( !reset_n) begin
|
if( !reset_n) begin
|
count=0;
|
count<=0;
|
clkdiv=0;
|
clkdiv<=0;
|
end
|
end
|
else begin
|
else begin
|
if( period==0 ) begin
|
if( period==0 ) begin
|
clkdiv<=0;
|
clkdiv<=0;
|
count<=0;
|
count<=0;
|
end
|
end
|
else if( count >= period ) begin
|
else if( count >= period ) begin
|
count <= 0;
|
count <= 0;
|
clkdiv = ~clkdiv;
|
clkdiv <= ~clkdiv;
|
end
|
end
|
else count <= count+1;
|
else count <= count+1;
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
| Line 190... |
Line 174... |
reg [16:0]poly17;
|
reg [16:0]poly17;
|
wire poly17_zero = poly17==0;
|
wire poly17_zero = poly17==0;
|
assign noise=poly17[16];
|
assign noise=poly17[16];
|
wire noise_clk;
|
wire noise_clk;
|
|
|
always @(posedge noise_clk or reset_n) begin
|
always @(posedge noise_clk or negedge reset_n) begin
|
if( !reset_n) begin
|
if( !reset_n) begin
|
poly17=0;
|
poly17<=0;
|
end
|
end
|
else begin
|
else begin
|
poly17={ poly17[0] ^ poly17[2] ^ poly17_zero, poly17[16:1] };
|
poly17<={ poly17[0] ^ poly17[2] ^ poly17_zero, poly17[16:1] };
|
end
|
end
|
end
|
end
|
|
|
SQM_CLK_DIVIDER #(5) ndiv( .clk(clk), .reset_n(reset_n),
|
SQM_CLK_DIVIDER #(5) ndiv( .clk(clk), .reset_n(reset_n),
|
.period(period), .div(noise_clk) );
|
.period(period), .div(noise_clk) );
|
| Line 215... |
Line 199... |
|
|
reg dir; // direction
|
reg dir; // direction
|
reg stop;
|
reg stop;
|
reg [3:0]prev_ctrl; // last control orders
|
reg [3:0]prev_ctrl; // last control orders
|
|
|
always @(posedge clk or reset_n) begin
|
always @(posedge clk or negedge reset_n) begin
|
if( !reset_n) begin
|
if( !reset_n) begin
|
gain=4'hF;
|
gain<=4'hF;
|
dir=0;
|
dir<=0;
|
prev_ctrl=0;
|
prev_ctrl<=0;
|
stop=1;
|
stop<=1;
|
end
|
end
|
else begin
|
else begin
|
if (ctrl!=prev_ctrl) begin
|
if (ctrl!=prev_ctrl) begin
|
prev_ctrl<=ctrl;
|
prev_ctrl<=ctrl;
|
if( ctrl[2] ) begin
|
if( ctrl[2] ) begin
|
