| Line 19... |
Line 19... |
Usage:
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Usage:
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PERIPHERAL AXI4_Lite_Master \\
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PERIPHERAL AXI4_Lite_Master \\
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basePortName=<name> \\
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basePortName=<name> \\
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address=<O_address> \\
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address=<O_address> \\
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data=<O_data> \\
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data=<O_data> \\
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write_enable=<O_write_enable> \\
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command_read=<O_command_read> \\
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command_read=<O_command_read> \\
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command_write=<O_command_write> \\
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command_write=<O_command_write> \\
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busy=<I_busy> \\
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busy=<I_busy> \\
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error=<I_error> \\
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error=<I_error> \\
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read=<I_read> \\
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read=<I_read> \\
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address_width=<N> \\
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address_width=<N> \\
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synchronous={True|False}
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synchronous={True|False} \\
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write_enable=<O_write_enable>|noWSTRB\n
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Where:
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Where:
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basePortName=<name>
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basePortName=<name>
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specifies the name used to construct the multiple AXI4-Lite signals
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specifies the name used to construct the multiple AXI4-Lite signals
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address=<O_address>
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address=<O_address>
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specifies the symbol used to set the address used for read and write
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specifies the symbol used to set the address used for read and write
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| Line 45... |
Line 45... |
data=<O_data>
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data=<O_data>
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specifies the symbol used to set the 32-bit data for write operations
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specifies the symbol used to set the 32-bit data for write operations
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Note: Four outputs to this address are required, starting with the MSB of
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Note: Four outputs to this address are required, starting with the MSB of
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the 32-bit value, See the examples for illustrations of how this
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the 32-bit value, See the examples for illustrations of how this
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works.
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works.
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write_enable=<O_write_enable>
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specifies the symbol used to set the 4 write enable bits
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command_read=<O_command_read>
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command_read=<O_command_read>
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specifies the symbol used to start the AXI4-Lite master core to issue a
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specifies the symbol used to start the AXI4-Lite master core to issue a
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read and store the received data
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read and store the received data
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command_write=<O_command_write>
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command_write=<O_command_write>
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specifies the symbol used to start the AXI4-Lite master core to issue a
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specifies the symbol used to start the AXI4-Lite master core to issue a
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| Line 70... |
Line 68... |
address_width=<N>
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address_width=<N>
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specifies the width of the 8-bit aligned address\n
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specifies the width of the 8-bit aligned address\n
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synchronous={True|False}
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synchronous={True|False}
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indicates whether or not he micro controller clock and the AXI4-Lite bus
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indicates whether or not he micro controller clock and the AXI4-Lite bus
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are synchronous
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are synchronous
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write_enable=<O_write_enable>
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optionally specify the symbol used to set the 4 write enable bits
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Note: This must be used if one or more of the slaves includes the
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optional WSTRB signals.
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noWSTRB
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indicates that the optional WSTRB signal should not be included
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Note: This must be specified if write_enable is not specified.\n
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Vivado Users:
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The peripheral creates a TCL script to facilitate turning the micro
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controller into an IP core. Look for a file with the name
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"vivado_<basePortName>.tcl".\n
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Example: Xilinx' AXI_DMA core has a 7-bit address range for its register
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Example: Xilinx' AXI_DMA core has a 7-bit address range for its register
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address map. The PERIPHERAL configuration statement to interface to this
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address map. The PERIPHERAL configuration statement to interface to this
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core would be:\n
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core would be:\n
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PERIPHERAL AXI4_Lite_Master \
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PERIPHERAL AXI4_Lite_Master \
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basePortName=myAxiDmaDevice \
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basePortName=myAxiDmaDevice \
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address=O_myAxiDmaDevice_address \
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address=O_myAxiDmaDevice_address \
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data=O_myAxiDmaDevice_data \
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data=O_myAxiDmaDevice_data \
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write_enable=O_myAxiDmaDevice_wen \
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command_read=O_myAxiDmaDevice_cmd_read \
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command_read=O_myAxiDmaDevice_cmd_read \
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command_write=O_myAxiDmaDevice_cmd_write \
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command_write=O_myAxiDmaDevice_cmd_write \
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busy=I_myAxiDmaDevice_busy \
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busy=I_myAxiDmaDevice_busy \
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error=I_myAxiDmaDevice_error \
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error=I_myAxiDmaDevice_error \
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read=I_myAxiDmaDevice_read \
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read=I_myAxiDmaDevice_read \
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address_width=7 \
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address_width=7 \
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synchronous=True\n
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synchronous=True \\
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write_enable=O_myAxiDmaDevice_wen\n
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To write to the memory master to slave start address, use the
|
To write to the memory master to slave start address, use the
|
following, where "start_address" is a 4-byte variable set elsewhere in the
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following, where "start_address" is a 4-byte variable set elsewhere in the
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program:\n
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program:\n
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; Set the 7-bit register address.
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; Set the 7-bit register address.
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0x18 .outport(O_myAxiDmaDevice_address)
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0x18 .outport(O_myAxiDmaDevice_address)
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| Line 164... |
Line 173... |
('command_write', r'O_\w+$', None, ),
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('command_write', r'O_\w+$', None, ),
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('data', r'O_\w+$', None, ),
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('data', r'O_\w+$', None, ),
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('read', r'I_\w+$', None, ),
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('read', r'I_\w+$', None, ),
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('busy', r'I_\w+$', None, ),
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('busy', r'I_\w+$', None, ),
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('error', r'I_\w+$', None, ),
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('error', r'I_\w+$', None, ),
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('noWSTRB', None, None, ),
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('synchronous', r'(True|False)$', bool, ),
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('synchronous', r'(True|False)$', bool, ),
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('write_enable', r'O_\w+$', None, ),
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('write_enable', r'O_\w+$', None, ),
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);
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);
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names = [a[0] for a in allowables];
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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for param_tuple in param_list:
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param = param_tuple[0];
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param = param_tuple[0];
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if param not in names:
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided (all parameters are required).
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# Ensure the required parameters are provided.
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for paramname in names:
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for paramname in (
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'address',
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'address_width',
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'basePortName',
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'command_read',
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'command_write',
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'data',
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'read',
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'busy',
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'error',
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'synchronous',
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):
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if not hasattr(self,paramname):
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# There are no optional parameters.
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# Ensure one and only one of the complementary optional values are set.
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if not hasattr(self,'write_enable') and not hasattr(self,'noWSTRB'):
|
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raise SSBCCException('One of "write_enable" or "noWSTRB" must be set at %s' % loc);
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if hasattr(self,'write_enable') and hasattr(self,'noWSTRB'):
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raise SSBCCException('Only one of "write_enable" or "noWSTRB" can be set at %s' % loc);
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self.noWSTRB = hasattr(self,'noWSTRB');
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# Temporary: Warning message
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# Temporary: Warning message
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if not self.synchronous:
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if not self.synchronous:
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raise SSBCCException('synchronous=False has not been validated yet');
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raise SSBCCException('synchronous=False has not been validated yet');
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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for signal in (
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for signal in (
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| Line 192... |
Line 218... |
( 'i_%s_awready', 1, 'input', ),
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( 'i_%s_awready', 1, 'input', ),
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( 'o_%s_awaddr', self.address_width, 'output', ),
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( 'o_%s_awaddr', self.address_width, 'output', ),
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( 'o_%s_wvalid', 1, 'output', ),
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( 'o_%s_wvalid', 1, 'output', ),
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( 'i_%s_wready', 1, 'input', ),
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( 'i_%s_wready', 1, 'input', ),
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( 'o_%s_wdata', 32, 'output', ),
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( 'o_%s_wdata', 32, 'output', ),
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( 'o_%s_wstrb', 4, 'output', ),
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( 'o_%s_wstrb', 4, 'output', ) if not self.noWSTRB else None,
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( 'i_%s_bresp', 2, 'input', ),
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( 'i_%s_bresp', 2, 'input', ),
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( 'i_%s_bvalid', 1, 'input', ),
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( 'i_%s_bvalid', 1, 'input', ),
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( 'o_%s_bready', 1, 'output', ),
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( 'o_%s_bready', 1, 'output', ),
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( 'o_%s_arvalid', 1, 'output', ),
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( 'o_%s_arvalid', 1, 'output', ),
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( 'i_%s_arready', 1, 'input', ),
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( 'i_%s_arready', 1, 'input', ),
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| Line 204... |
Line 230... |
( 'i_%s_rvalid', 1, 'input', ),
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( 'i_%s_rvalid', 1, 'input', ),
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( 'o_%s_rready', 1, 'output', ),
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( 'o_%s_rready', 1, 'output', ),
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( 'i_%s_rdata', 32, 'input', ),
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( 'i_%s_rdata', 32, 'input', ),
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( 'i_%s_rresp', 2, 'input', ),
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( 'i_%s_rresp', 2, 'input', ),
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):
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):
|
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if not signal:
|
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continue
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thisName = signal[0] % self.basePortName;
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thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddSignal('s__%s__address' % self.basePortName, self.address_width, loc);
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config.AddSignal('s__%s__address' % self.basePortName, self.address_width, loc);
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config.AddSignal('s__%s__rd' % self.basePortName, 1, loc);
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config.AddSignal('s__%s__rd' % self.basePortName, 1, loc);
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config.AddSignal('s__%s__wr' % self.basePortName, 1, loc);
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config.AddSignal('s__%s__wr' % self.basePortName, 1, loc);
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| Line 220... |
Line 248... |
),loc);
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),loc);
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self.ix_data = config.NOutports();
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self.ix_data = config.NOutports();
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config.AddOutport((self.data,False,
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config.AddOutport((self.data,False,
|
# empty list -- disable normal output port signal generation
|
# empty list -- disable normal output port signal generation
|
),loc);
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),loc);
|
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if not self.noWSTRB:
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config.AddOutport((self.write_enable,False,
|
config.AddOutport((self.write_enable,False,
|
('o_%s_wstrb' % self.basePortName, 4, 'data', ),
|
('o_%s_wstrb' % self.basePortName, 4, 'data', ),
|
),loc);
|
),loc);
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config.AddOutport((self.command_read,True,
|
config.AddOutport((self.command_read,True,
|
('s__%s__rd' % self.basePortName, 1, 'strobe', ),
|
('s__%s__rd' % self.basePortName, 1, 'strobe', ),
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| Line 265... |
Line 294... |
):
|
):
|
body = re.sub(subpair[0],subpair[1],body);
|
body = re.sub(subpair[0],subpair[1],body);
|
body = self.GenVerilogFinal(config,body);
|
body = self.GenVerilogFinal(config,body);
|
fp.write(body);
|
fp.write(body);
|
|
|
No newline at end of file
|
No newline at end of file
|
|
# Write the TCL script to facilitate creating Vivado IP for the port.
|
|
vivadoFile = os.path.join(os.path.dirname(self.peripheralFile),'vivado_AXI4_Lite_Bus.py');
|
|
execfile(vivadoFile,globals());
|
|
WriteTclScript('master',self.basePortName,self.address_width,noWSTRB=self.noWSTRB);
|
|
|
No newline at end of file
|
No newline at end of file
|
