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//
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//
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// PERIPHERAL stepper_motor: @NAME@
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// PERIPHERAL stepper_motor: @NAME@
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// Copyright 2015, Sinclair R.F., Inc.
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// Copyright 2015, Sinclair R.F., Inc.
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//
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//
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// Assemble the byes of the control word from the input bytes.
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@MASTER_BEGIN@
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@MASTER_BEGIN@
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localparam L__RATEMETHOD_MINUS_1 = @RATEMETHOD@ - 1;
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localparam L__RATEMETHOD_MINUS_1 = @RATEMETHOD@ - 1;
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localparam L__NBITS_RATEMETHOD = clog2(L__RATEMETHOD_MINUS_1);
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localparam L__NBITS_RATEMETHOD = clog2(L__RATEMETHOD_MINUS_1);
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@MASTER_END@
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// Assemble the byes of the control word from the input bytes.
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reg [@CONTROL_WIDTH@-1:0] s__input_control_word = {(@CONTROL_WIDTH@){1'b0}};
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reg [@CONTROL_WIDTH@-1:0] s__input_control_word = {(@CONTROL_WIDTH@){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__input_control_word <= {(@CONTROL_WIDTH@){1'b0}};
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s__input_control_word <= {(@CONTROL_WIDTH@){1'b0}};
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else if (s_outport && (s_T == 8'd@IX_OUTCONTROL@))
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else if (s_outport && (s_T == 8'd@IX_OUTCONTROL@))
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s__input_control_word[@DW@*((@MODE_WIDTH@+@DWM1@)/@DW@)+:@COUNT_WIDTH@]
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s__input_control_word[@DW@*((@MODE_WIDTH@+@DWM1@)/@DW@)+:@COUNT_WIDTH@]
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@OUTMODE_BEGIN@
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@OUTMODE_BEGIN@
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, s__input_control_word[0+:@MODE_WIDTH@]
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, s__input_control_word[0+:@MODE_WIDTH@]
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@OUTMODE_END@
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@OUTMODE_END@
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};
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};
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@MASTER_END@
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// Instantiate the control word FIFO and operate its input side.
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// Instantiate the control word FIFO and operate its input side.
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reg s__FIFO_wr = 1'b0;
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reg s__FIFO_wr = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__FIFO_wr <= 1'b0;
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s__FIFO_wr <= 1'b0;
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else
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else
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s__FIFO_in_addr <= s__FIFO_in_addr + { @NBITS_FIFO_DEPTH@'d0, s__FIFO_wr };
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s__FIFO_in_addr <= s__FIFO_in_addr + { @NBITS_FIFO_DEPTH@'d0, s__FIFO_wr };
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reg [@CONTROL_WIDTH_PACKED@-1:0] s__FIFO[@FIFO_DEPTH@-1:0];
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reg [@CONTROL_WIDTH_PACKED@-1:0] s__FIFO[@FIFO_DEPTH@-1:0];
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (s__FIFO_wr)
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if (s__FIFO_wr)
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s__FIFO[s__FIFO_in_addr[0+:@NBITS_FIFO_DEPTH@]] <= s__input_control_word_packed;
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s__FIFO[s__FIFO_in_addr[0+:@NBITS_FIFO_DEPTH@]] <= @S__INPUT_CONTROL_WORD_PACKED@;
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// Operate the output side of the FIFO and translate the packed controls into
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// Operate the output side of the FIFO and translate the packed controls into
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// individual signals.
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// individual signals.
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reg s__FIFO_rd = 1'b0;
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reg s__FIFO_rd = 1'b0;
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reg [@NBITS_FIFO_DEPTH@:0] s__FIFO_out_addr = {(@NBITS_FIFO_DEPTH@+1){1'b0}};
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reg [@NBITS_FIFO_DEPTH@:0] s__FIFO_out_addr = {(@NBITS_FIFO_DEPTH@+1){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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