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################################################################################
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################################################################################
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#
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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# Copyright 2012-2015, Sinclair R.F., Inc.
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#
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#
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################################################################################
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################################################################################
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import re
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import re
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//
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//
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generate
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generate
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reg [C_PC_WIDTH-1:0] s__PC_s[1:0];
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reg [C_PC_WIDTH-1:0] s__PC_s[1:0];
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reg [8:0] s__opcode_s = 9'h000;
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reg [8:0] s__opcode_s = 9'h000;
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reg [7*8-1:0] s__opcode_name;
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reg [7*8-1:0] s__opcode_name;
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reg s__interrupt_s = 1'b0;
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reg s__interrupted_s = 1'b0;
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initial begin
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initial begin
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s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
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end
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end
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always @ (posedge i_clk) begin
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always @ (posedge i_clk) begin
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s__PC_s[0] <= s_PC;
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s__PC_s[0] <= s_PC;
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s__PC_s[1] <= s__PC_s[0];
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s__PC_s[1] <= s__PC_s[0];
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s__interrupt_s <= s_interrupt;
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s__interrupted_s <= s_interrupted;
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s__opcode_s <= s_opcode;
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s__opcode_s <= s_opcode;
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display_trace({ s__PC_s[1], s__opcode_s, s_Np_stack_ptr, 1'b1, s_N, 1'b1, s_T, 1'b1, s_R, s_R_stack_ptr });
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display_trace({ s__interrupt_s, s__interrupted_s, s__PC_s[1], s__opcode_s, s_Np_stack_ptr, 1'b1, s_N, 1'b1, s_T, 1'b1, s_R, s_R_stack_ptr });
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end
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end
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endgenerate
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endgenerate
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""";
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""";
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if not config.InterruptVector():
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for replace in ('s_interrupt','s_interrupted',):
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body = re.sub(replace+';','1\'b0;',body);
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body = re.sub(r'\bs__','s__trace__',body);
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body = re.sub(r'\bs__','s__trace__',body);
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fp.write(body);
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fp.write(body);
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No newline at end of file
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No newline at end of file
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