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################################################################################
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################################################################################
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#
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#
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# Copyright 2012, Sinclair R.F., Inc.
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# Copyright 2012-2015, Sinclair R.F., Inc.
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#
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#
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# Verilog generation functions.
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# Verilog generation functions.
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#
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#
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################################################################################
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################################################################################
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#
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#
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# Generate input and output core names.
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# Generate input and output core names.
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#
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#
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################################################################################
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################################################################################
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def doFillCommand(fillCommand,fpOutCore,config):
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"""
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Do core-specific fill commands for the "..@SSBCC@ <fillCommand>" lines.
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"""
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# functions and tasks
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if fillCommand == "functions":
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genFunctions(fpOutCore,config);
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# inports
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elif fillCommand == 'inports':
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genInports(fpOutCore,config);
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# interrupt conditionals
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elif fillCommand == 'interrupt__s_math_rotate':
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if config.InterruptVector():
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fpOutCore.write(""" if (s_interrupt || s_interrupted)
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s_math_rotate = s_T;
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else""");
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elif fillCommand == 'interrupt__s_opcode':
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if config.InterruptVector():
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fpOutCore.write(""" if (s_interrupted) begin
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// nop
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end else if (s_interrupt) begin
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s_return = C_RETURN_INC;
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end else""");
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# localparam
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elif fillCommand == 'localparam':
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genLocalParam(fpOutCore,config);
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# module
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elif fillCommand == 'module':
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genModule(fpOutCore,config);
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# outports
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elif fillCommand == 'outports':
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genOutports(fpOutCore,config);
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# "s_PC_next" body
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elif fillCommand == 's_PC_next':
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genSPCnext(fpOutCore,config);
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# "s_R_pre" body
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elif fillCommand == 's_R_pre':
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genSRpre(fpOutCore,config);
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# additional signals
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elif fillCommand == 'signals':
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genSignals(fpOutCore,config);
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# error
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else:
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print 'WARNING: Unimplemented command ' + fillCommand;
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def genCoreName():
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def genCoreName():
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"""
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"""
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Return the name of the file to use for the processor core.
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Return the name of the file to use for the processor core.
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"""
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"""
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return 'core.v';
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return 'core.v';
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Line 93... |
on the ssbcc command line
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on the ssbcc command line
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display_opcode human-readable version of the opcode suitable for
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display_opcode human-readable version of the opcode suitable for
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waveform viewers
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waveform viewers
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display_trace when the trace or monitor_stack peripherals are included
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display_trace when the trace or monitor_stack peripherals are included
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"""
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"""
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def DisableInterrupt(body):
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for replace in ('s_interrupt','s_interrupted',):
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replace = '\(' + replace + '\)';
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while re.search(replace,body):
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body = re.sub(replace,'(1\'b0)',body);
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return body;
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if 'display_opcode' in config.functions:
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if 'display_opcode' in config.functions:
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displayOpcodePath = os.path.join(config.Get('corepath'),'display_opcode.v');
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displayOpcodePath = os.path.join(config.Get('corepath'),'display_opcode.v');
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fpDisplayOpcode = open(displayOpcodePath,'rt');
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fpDisplayOpcode = open(displayOpcodePath,'rt');
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if not fpDisplayOpcode:
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if not fpDisplayOpcode:
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raise Exception('Program Bug -- "%s" not found' % displayOpcodePath);
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raise Exception('Program Bug -- "%s" not found' % displayOpcodePath);
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body = fpDisplayOpcode.read();
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body = fpDisplayOpcode.read();
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fpDisplayOpcode.close();
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fpDisplayOpcode.close();
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if not config.InterruptVector():
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body = DisableInterrupt(body);
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fp.write(body);
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fp.write(body);
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if ('clog2' in config.functions) and config.Get('define_clog2'):
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if ('clog2' in config.functions) and config.Get('define_clog2'):
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fp.write("""
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fp.write("""
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// Use constant function instead of builtin $clog2.
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// Use constant function instead of builtin $clog2.
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function integer clog2;
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function integer clog2;
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Line 129... |
fpDisplayTrace = open(displayTracePath,'rt');
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fpDisplayTrace = open(displayTracePath,'rt');
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if not fpDisplayTrace:
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if not fpDisplayTrace:
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raise Exception('Program Bug -- "%s" not found' % displayTracePath);
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raise Exception('Program Bug -- "%s" not found' % displayTracePath);
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body = fpDisplayTrace.read();
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body = fpDisplayTrace.read();
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fpDisplayTrace.close();
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fpDisplayTrace.close();
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if not config.InterruptVector():
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body = DisableInterrupt(body);
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fp.write(body);
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fp.write(body);
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def genInports(fp,config):
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def genInports(fp,config):
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"""
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"""
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Generate the logic for the input signals.
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Generate the logic for the input signals.
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Line 214... |
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def genLocalParam(fp,config):
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def genLocalParam(fp,config):
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"""
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"""
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Generate the localparams for implementation-specific constants.
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Generate the localparams for implementation-specific constants.
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"""
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"""
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fp.write('localparam C_PC_WIDTH = %4d;\n' % CeilLog2(config.Get('nInstructions')['length']));
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pcWidth = CeilLog2(config.Get('nInstructions')['length']);
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fp.write('localparam C_PC_WIDTH = %4d;\n' % pcWidth);
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fp.write('localparam C_RETURN_PTR_WIDTH = %4d;\n' % CeilLog2(config.Get('return_stack')));
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fp.write('localparam C_RETURN_PTR_WIDTH = %4d;\n' % CeilLog2(config.Get('return_stack')));
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fp.write('localparam C_DATA_PTR_WIDTH = %4d;\n' % CeilLog2(config.Get('data_stack')));
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fp.write('localparam C_DATA_PTR_WIDTH = %4d;\n' % CeilLog2(config.Get('data_stack')));
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fp.write('localparam C_RETURN_WIDTH = (C_PC_WIDTH <= 8) ? 8 : C_PC_WIDTH;\n');
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fp.write('localparam C_RETURN_WIDTH = (C_PC_WIDTH <= 8) ? 8 : C_PC_WIDTH;\n');
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def genMemories(fp,fpMemFile,config,programBody):
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def genMemories(fp,fpMemFile,config,programBody):
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Line 804... |
for jx in range(len(thisPort)):
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for jx in range(len(thisPort)):
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signal = thisPort[jx];
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signal = thisPort[jx];
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signalName = signal[0];
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signalName = signal[0];
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signalWidth = signal[1];
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signalWidth = signal[1];
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signalType = signal[2];
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signalType = signal[2];
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signalInit = '%d\'d0' % signalWidth if len(signal)==3 else signal[3];
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signalInit = 0 if len(signal)==3 else signal[3];
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signalInit = InitSignal(signalWidth,signalInit)
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if signalType == 'data':
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if signalType == 'data':
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fp.write('initial %s = %s;\n' % (signalName,signalInit,));
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fp.write('initial %s = %s;\n' % (signalName,signalInit,));
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if bitWidth > 0:
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if bitWidth > 0:
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bitName += ', ';
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bitName += ', ';
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bitInit += ', '
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bitInit += ', '
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Line 862... |
maxLength = len(signalName);
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maxLength = len(signalName);
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maxLength = maxLength + 12;
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maxLength = maxLength + 12;
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for thisSignal in config.signals:
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for thisSignal in config.signals:
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signalName = thisSignal[0];
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signalName = thisSignal[0];
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signalWidth = thisSignal[1];
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signalWidth = thisSignal[1];
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signalInit = "%d'd0" % signalWidth if len(thisSignal) < 3 else thisSignal[2];
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signalInit = 0 if len(thisSignal)==2 else thisSignal[2];
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outString = 'reg ';
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outString = 'reg ';
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if signalWidth == 1:
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if signalWidth == 1:
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outString += ' ';
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outString += ' ';
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elif signalWidth <= 10:
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elif signalWidth <= 10:
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outString += (' [%d:0] ' % (signalWidth-1));
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outString += (' [%d:0] ' % (signalWidth-1));
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else:
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else:
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outString += ('[%2d:0] ' % (signalWidth-1));
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outString += ('[%2d:0] ' % (signalWidth-1));
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outString += signalName;
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outString += signalName;
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if signalInit != None:
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if signalInit != None:
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outString += ' '*(maxLength-len(outString));
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outString += ' '*(maxLength-len(outString));
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outString += ' = ' + signalInit;
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outString += ' = ' + InitSignal(signalWidth,signalInit);
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outString += ';\n'
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outString += ';\n'
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fp.write(outString);
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fp.write(outString);
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def genSPCnext(fp,config):
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"""
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Write the logic to generate the next PC address.\n
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Note: This signal depends on whether or not interrupts are enabled.
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"""
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pcWidth = CeilLog2(config.Get('nInstructions')['length']);
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fp.write("reg [C_PC_WIDTH-1:0] s_PC_next;\n");
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fp.write("always @ (*)\n");
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if config.InterruptVector():
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format_pc_addr = "%d\'h%%0%dx" % (pcWidth,(pcWidth+3)/4,);
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fp.write(" if (s_interrupt)\n");
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fp.write(" s_PC_next = %s;\n" % (format_pc_addr % config.InterruptVector()));
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fp.write(" else");
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fp.write(" case (s_bus_pc)\n");
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fp.write(" C_BUS_PC_NORMAL:\n");
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fp.write(" s_PC_next = s_PC_plus1;\n");
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fp.write(" C_BUS_PC_JUMP:\n");
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fp.write(" s_PC_next = s_PC_jump;\n");
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fp.write(" C_BUS_PC_RETURN:\n");
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fp.write(" s_PC_next = s_R[0+:C_PC_WIDTH];\n");
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fp.write(" default:\n");
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fp.write(" s_PC_next = s_PC_plus1;\n");
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fp.write(" endcase\n");
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def genSRpre(fp,config):
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"""
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Write the logic to select the value to be put onto the return stack.\n
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Note: This also captures the pc value to be put onto the return stack as
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part of interrupt handling.
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"""
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data_width = config.Get('data_width');
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pcWidth = CeilLog2(config.Get('nInstructions')['length']);
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if pcWidth <= data_width:
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assignT = "s_T";
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else:
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assignT = "{ {(C_PC_WIDTH-%d){1'b0}}, s_T }" % data_width;
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if pcWidth < data_width:
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assignPC = "{ {(%d-C_PC_WIDTH){1'b0}}, %%s }" % data_width;
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else:
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assignPC = "%s";
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if config.InterruptVector():
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fp.write("reg [C_RETURN_WIDTH-1:0] s_PC_s = {(C_RETURN_WIDTH){1'b0}};\n");
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fp.write("always @ (posedge i_clk)\n");
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fp.write(" if (i_rst)\n");
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fp.write(" s_PC_s <= {(C_RETURN_WIDTH){1'b0}};\n");
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fp.write(" else\n");
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fp.write(" s_PC_s <= s_PC;\n");
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fp.write("\n");
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fp.write("reg [C_RETURN_WIDTH-1:0] s_R_pre;\n");
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fp.write("always @ (*)\n");
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if config.InterruptVector():
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fp.write(" if (s_interrupt)\n");
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fp.write(" s_R_pre = %s;\n" % (assignPC % "s_PC_s"));
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fp.write(" else");
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fp.write(" case (s_bus_r)\n");
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fp.write(" C_BUS_R_T:\n");
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fp.write(" s_R_pre = %s;\n" % assignT);
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fp.write(" C_BUS_R_PC:\n");
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fp.write(" s_R_pre = %s;\n" % (assignPC % "s_PC_plus1"));
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fp.write(" default:\n");
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fp.write(" s_R_pre = %s;\n" % assignT);
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fp.write(" endcase\n");
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def genUserHeader(fp,user_header):
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def genUserHeader(fp,user_header):
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"""
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"""
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Copy the user header to the output module.
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Copy the user header to the output module.
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"""
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"""
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for ix in range(len(user_header)):
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for ix in range(len(user_header)):
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