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#/* *****************************************************************************
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# * title: uart_16550_rll module *
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# * description: RS232 Protocol 16550D uart (mostly supported) *
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# * languages: systemVerilog *
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# * *
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# * Copyright (C) 2010 miyagi.hiroshi *
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# * *
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# * This library is free software; you can redistribute it and/or *
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# * modify it under the terms of the GNU Lesser General Public *
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# * License as published by the Free Software Foundation; either *
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# * version 2.1 of the License, or (at your option) any later version. *
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# * *
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# * This library is distributed in the hope that it will be useful, *
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# * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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# * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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# * Lesser General Public License for more details. *
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# * *
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# * You should have received a copy of the GNU Lesser General Public *
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# * License along with this library; if not, write to the Free Software *
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# * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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# * *
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# * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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# * from http://www.gnu.org/licenses/lgpl.txt *
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# *****************************************************************************
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# * redleaflogic,ltd *
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# * miyagi.hiroshi@redleaflogic.biz *
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# * $Id: uart_test.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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# ***************************************************************************** */
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.SUFFIXES :
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.SUFFIXES : .v .sv .vcd .log
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all: uart_test.log
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align = ALIGN_4B
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.sv.log:
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vlog -f uart_rtl.list -sv +acc=rn +define+${align}+
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vlog -f uart_be.list -sv +acc=rn +define+${align}+
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vsim -i top < modelSim.in
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mv transcript uart_test_${align}.log
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mv uart_16550_rll.dump uart_test_a_${align}.dump
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work:
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vlib work
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clean:
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- \rm -rf ./work *.vcd *.wlf *.dump *.log
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