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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 243 and 246

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Rev 243 Rev 246
Line 148... Line 148... 
        reg jsr;
 
        reg jsr;
 
        reg tsx;
 
        reg tsx;
 
        reg txs;
 
        reg txs;
 
        reg nop;
 
        reg nop;
 
 
 
 
 
 
 
        reg invalid;
 
 
 
 
 
        wire [ADDR_SIZE_:0] next_pc;      // a simple logic to add one to the PC
 
        wire [ADDR_SIZE_:0] next_pc;      // a simple logic to add one to the PC
 
        assign next_pc = pc + 13'b0000000000001;
 
        assign next_pc = pc + 13'b0000000000001;
 
 
 
 
 
        wire [DATA_SIZE:0] sp_plus_one;          // simple adder and subtracter for the stack pointer
 
        wire [DATA_SIZE:0] sp_plus_one;          // simple adder and subtracter for the stack pointer
 
        assign sp_plus_one = {1'b1, sp[7:0] + 8'b000000001};
 
        assign sp_plus_one = {1'b1, sp[7:0] + 8'b000000001};
Line 336... Line 338... 
                                                else if (pla || plp) begin
 
                                                else if (pla || plp) begin
 
                                                        pc <= pc;
 
                                                        pc <= pc;
 
                                                        address <= sp;
 
                                                        address <= sp;
 
                                                        mem_rw <= MEM_READ;
 
                                                        mem_rw <= MEM_READ;
 
                                                end
 
                                                end
 
 
 
                                                else if (invalid) begin
 
 
 
                                                        address <= pc;
 
 
 
                                                        mem_rw <= MEM_READ;
 
 
 
                                                end
 
                                                else begin // jsr
 
                                                else begin // jsr
 
                                                        address <= sp;
 
                                                        address <= sp;
 
                                                        mem_rw <= MEM_READ;
 
                                                        mem_rw <= MEM_READ;
 
                                                        temp_addr <= {{5{1'b0}}, data_in};
 
                                                        temp_addr <= {{5{1'b0}}, data_in};
 
                                                        pc <= next_pc;
 
                                                        pc <= next_pc;
Line 524... Line 530... 
                                                address <= address_plus_index;
 
                                                address <= address_plus_index;
 
                                                temp_addr[12:8] <= data_in;
 
                                                temp_addr[12:8] <= data_in;
 
                                                mem_rw <= MEM_READ;
 
                                                mem_rw <= MEM_READ;
 
                                        end
 
                                        end
 
                                end
 
                                end
 
                                PUSH_PCH: begin
 
                                PUSH_PCH: begin // this is probably wrong
 
                                        pc <= pc;
 
                                        pc <= pc;
 
                                        address <= sp_minus_one;
 
                                        address <= sp_minus_one;
 
                                        data_out <= pc[7:0];
 
                                        data_out <= pc[7:0];
 
                                        mem_rw <= MEM_WRITE;
 
                                        mem_rw <= MEM_WRITE;
 
                                        sp <= sp_minus_one;
 
                                        sp <= sp_minus_one;
Line 614... Line 620... 
                alu_opcode = 8'h00;
 
                alu_opcode = 8'h00;
 
                alu_a = 8'h00;
 
                alu_a = 8'h00;
 
                alu_enable = 1'b0;
 
                alu_enable = 1'b0;
 
                next_state = RESET; // these lines prevents latches
 
                next_state = RESET; // these lines prevents latches
 
 
 
 
 
                case (state)
 
                if (invalid == 1'b1) begin
 
 
 
                        next_state = FETCH_OP;
 
 
 
                end
 
 
 
                else case (state)
 
                        RESET: begin
 
                        RESET: begin
 
                                if (rst_counter == 3'd6) begin
 
                                if (rst_counter == 3'd6) begin
 
                                        next_state = FETCH_OP;
 
                                        next_state = FETCH_OP;
 
                                end
 
                                end
 
                        end
 
                        end
Line 929... Line 938... 
                jsr = 1'b0;
 
                jsr = 1'b0;
 
                tsx = 1'b0;
 
                tsx = 1'b0;
 
                txs = 1'b0;
 
                txs = 1'b0;
 
                nop = 1'b0;
 
                nop = 1'b0;
 
 
 
 
 
 
 
                invalid = 1'b0;
 
 
 
 
 
                case (ir)
 
                case (ir)
 
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP,
 
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP,
 
                        TAY_IMP, TXA_IMP, TYA_IMP: begin
 
                        TAY_IMP, TXA_IMP, TYA_IMP: begin
 
                                implied = 1'b1;
 
                                implied = 1'b1;
 
                        end
 
                        end
Line 1110... Line 1121... 
                        PLP_IMP: begin
 
                        PLP_IMP: begin
 
                                plp = 1'b1;
 
                                plp = 1'b1;
 
                        end
 
                        end
 
                        JSR_ABS: begin
 
                        JSR_ABS: begin
 
                                jsr = 1'b1;
 
                                jsr = 1'b1;
 
 
 
                                jump = 1'b1;
 
                        end
 
                        end
 
                        TSX_IMP: begin
 
                        TSX_IMP: begin
 
                                tsx = 1'b1;
 
                                tsx = 1'b1;
 
                        end
 
                        end
 
                        TXS_IMP: begin
 
                        TXS_IMP: begin
Line 1121... Line 1133... 
                        end
 
                        end
 
                        default: begin
 
                        default: begin
 
                                index_is_x = 1'b1;
 
                                index_is_x = 1'b1;
 
                                //$write("state : %b", state);
 
                                //$write("state : %b", state);
 
                                if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
 
                                if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
 
 
 
                                        invalid = 1'b1;
 
                                        //$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
 
                                        //$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
 
                                        //$finish();
 
                                        //$finish();
 
                                end
 
                                end
 
                        end
 
                        end
 
                endcase
 
                endcase

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