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[/] [tcp_socket/] [trunk/] [TCPIP.rst] - Diff between revs 2 and 3
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Configuration
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Configuration
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=============
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=============
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The following parameters can be configured at compile time within source/server.h:
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The following parameters can be configured at compile time within source/server.h:
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+ Local Ethernet MAC address
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+ Local Ethernet MAC address (default: 0x000102030405)
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+ Local IP Address
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+ Local IP Address (default: 192.168.1.1)
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+ Local TCP Port number
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+ Local TCP Port number (default: 80 HTTP)
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Compile
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Compile
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=======
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=======
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Compile into a Verilog module (server.v) using the following command::
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Compile into a Verilog module (server.v) using the following command::
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$ chip2/c2verilog source/server.v
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$ chip2/c2verilog source/server.v
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Interface
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Interface
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=========
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=========
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::
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+-----------+
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| SERVER |
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+-----------+
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ethernet_rx [15:0] >===> >===> output_socket [15:0]
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ethernet_tx [15:0] <===< <===< input_socket [15:0]
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+-----------+
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Ethernet Interface
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Ethernet Interface
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------------------
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------------------
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The Ethernet interface consists of two streams of data:
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The Ethernet interface consists of two streams of data:
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