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For Xilinx, four output bits can be computed in each slice. Thus, the number of slices is given by:
 
For Xilinx, four output bits can be computed in each slice. Thus, the number of slices is given by:
 
\begin{align}
 
\begin{align}
 
        N_{\text{Slices}} = \ceil{\frac{\text{input\_word\_size}+2}{4}}
 
        N_{\text{Slices}} = \ceil{\frac{\text{input\_word\_size}+2}{4}}
 
\end{align}
 
\end{align}
 
The slice usage is independent of the operation performed. If a slice is not fully utilized, the remaining LUTs can still be used for other functionallities.
 
The slice usage is independent of the operation performed. If a slice is not fully utilized, the remaining LUTs can still be used for other functionalities.
 
 
 
 
 
\section{Performance}
 
\section{Performance}
 
 
 
 
 
To estimate the performance, the maximum clock frequencies ($f_\text{max}$) were obtained by synthesis experiments for Altera Stratix~IV (EP4SGX230KF40C2) using Quartus-II~10.1 and Xilinx Virtex~6 (XC6VLX75T-2FF484) using ISE 13.4, both after place \& route. The resulting clock frequencies with output word sizes from 16 up to 64\,bit are shown in Table~\ref{tab:performance}.
 
To estimate the performance, the maximum clock frequencies ($f_\text{max}$) were obtained by synthesis experiments for Altera Stratix~IV (EP4SGX230KF40C2) using Quartus-II~10.1 and Xilinx Virtex~6 (XC6VLX75T-2FF484) using ISE 13.4, both after place \& route. The resulting clock frequencies with output word sizes from 16 up to 64\,bit are shown in Table~\ref{tab:performance}.
 
 
 
 

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