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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_defines.vh] - Diff between revs 61 and 66
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| Rev 61 |
Rev 66 |
| Line 351... |
Line 351... |
`define CSR_DBCTRL 10'h01C
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`define CSR_DBCTRL 10'h01C
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`define CSR_DBSTAT 10'h01D
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`define CSR_DBSTAT 10'h01D
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`define CSR_CAS 10'h02C
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`define CSR_CAS 10'h02C
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`define CSR_TVEC 10'b00000110???
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`define CSR_TVEC 10'b00000110???
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`define CSR_IM_STACK 10'h040
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`define CSR_IM_STACK 10'h040
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`define CSR_OL_STACK 10'h041
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`define CSR_ODL_STACK 10'h041
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`define CSR_PL_STACK 10'h042
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`define CSR_PL_STACK 10'h042
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`define CSR_RS_STACK 10'h043
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`define CSR_RS_STACK 10'h043
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`define CSR_STATUS 10'h044
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`define CSR_STATUS 10'h044
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`define CSR_BRS_STACK 10'h046
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`define CSR_BRS_STACK 10'h046
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`define CSR_EPC0 10'h048
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`define CSR_EPC0 10'h048
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| Line 459... |
Line 459... |
`define FORW_BRANCH 1'b0
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`define FORW_BRANCH 1'b0
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`define BACK_BRANCH 1'b1
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`define BACK_BRANCH 1'b1
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`define DRAMSLOT_AVAIL 3'b000
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`define DRAMSLOT_AVAIL 3'b000
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`define DRAMSLOT_BUSY 3'b001
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`define DRAMSLOT_BUSY 3'b001
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`define DRAMSLOT_BUSY2 3'b010
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`define DRAMSLOT_REQBUS 3'b101
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`define DRAMSLOT_REQBUS 3'b101
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`define DRAMSLOT_HASBUS 3'b110
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`define DRAMSLOT_HASBUS 3'b110
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`define DRAMREQ_READY 3'b111
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`define DRAMREQ_READY 3'b111
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`define INV 1'b0
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`define INV 1'b0
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