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Line 287... |
When HOLD is no longer needed, it should just be turned low and an extra clock cycle should be waited on for it to return to RESET state
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When HOLD is no longer needed, it should just be turned low and an extra clock cycle should be waited on for it to return to RESET state
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When RESET is held low, the processor will execute. It takes 3 clock cycles for the processor to "catch up" to actually executing instructions
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When RESET is held low, the processor will execute. It takes 3 clock cycles for the processor to "catch up" to actually executing instructions
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Register order:
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The order of registers is read from left to right with left being the most significant bit of the 16-bit opcode.
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So for instance,
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0101_*000*0_0*111*_0010 is `mov [r0], IP/r7`. The register portions of the opcode are surrounded by astericks
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Implemented opcode list:
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Implemented opcode list:
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legend:
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legend:
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r = register choice
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r = register choice
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| Line 299... |
Line 302... |
C = conditional portion
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C = conditional portion
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s = segment register choice
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s = segment register choice
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i = immediate data
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i = immediate data
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N = not used
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N = not used
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o = opcode choice (for groups)
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o = opcode choice (for groups)
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_ = space for readability
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0000 rrrC iiii iiii
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0000_rrrC_iiii_iiii
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mov reg, immediate
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mov reg, immediate
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0001 rrrC iiii iiii
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0001_rrrC_iiii_iiii
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mov [reg], immediate
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mov [reg], immediate
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group 3 comparions
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group 3 comparions
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0011 rrrC Crrr Nooo
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0011_rrrC_Crrr_Nooo
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opcode choices
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opcode choices
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000: is greater than reg1,reg2 (TR=reg1>reg2)
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000: is greater than reg1,reg2 (TR=reg1>reg2)
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001: is greater or equal to reg,reg
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001: is greater or equal to reg,reg
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010: is less than reg,reg
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010: is less than reg,reg
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011: is less than or equal to reg,reg
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011: is less than or equal to reg,reg
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| Line 319... |
Line 323... |
101: is not equal to reg,reg
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101: is not equal to reg,reg
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110: equals 0 reg
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110: equals 0 reg
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111: not equals 0 reg
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111: not equals 0 reg
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group 4 bitwise
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group 4 bitwise
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0100 rrrC Crrr Nooo
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0100_rrrC_Crrr_Nooo
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opcode choices
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opcode choices
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000: and reg1,reg2 (reg1=reg1 and reg2)
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000: and reg1,reg2 (reg1=reg1 and reg2)
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001: or reg, reg
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001: or reg, reg
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010: xor reg,reg
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010: xor reg,reg
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011: not reg1,reg2 (reg1=not reg2)
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011: not reg1,reg2 (reg1=not reg2)
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| Line 331... |
Line 335... |
101: right shift reg,reg
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101: right shift reg,reg
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110: rotate right reg,reg
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110: rotate right reg,reg
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111: rotate left reg,reg
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111: rotate left reg,reg
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group 5 misc
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group 5 misc
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0101 rrrC CRRR sooo
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0101_rrrC_CRRR_sooo
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opcode choices:
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opcode choices:
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000: subgroup 5-0
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000: subgroup 5-0
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RRR choices:
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RRR choices:
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000: push reg
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000: push reg
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001: pop reg
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001: pop reg
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001: mov reg, reg
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001: mov reg, reg
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010: mov reg, [reg]
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011: mov [reg], reg
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