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[/] [tinycpu/] [trunk/] [src/] [core.vhd] - Diff between revs 24 and 25

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Rev 24 Rev 25
Line 97... Line 97... 
  signal CarrySS: std_logic;
 
  signal CarrySS: std_logic;
 
  signal IPAddend: std_logic_vector(7 downto 0);
 
  signal IPAddend: std_logic_vector(7 downto 0);
 
  signal SPAddend: std_logic_vector(7 downto 0);
 
  signal SPAddend: std_logic_vector(7 downto 0);
 
  signal IPCarryOut: std_logic_vector(7 downto 0);
 
  signal IPCarryOut: std_logic_vector(7 downto 0);
 
  signal CSCarryOut: std_logic_vector(7 downto 0);
 
  signal CSCarryOut: std_logic_vector(7 downto 0);
 
 
 
  signal SPCarryOut: std_logic_vector(7 downto 0);
 
 
 
  signal SSCarryOut: std_logic_vector(7 downto 0);
 
 
 
 
 
  --register signals
 
  --register signals
 
  signal regWE:regwritetype;
 
  signal regWE:regwritetype;
 
  signal regIn: regdatatype;
 
  signal regIn: regdatatype;
 
  signal regOut: regdatatype;
 
  signal regOut: regdatatype;
 
  --fetch signals
 
  --fetch signals
 
  signal fetchEN: std_logic;
 
  signal fetchEN: std_logic;
 
  signal IR: std_logic_vector(15 downto 0);
 
  signal IR: std_logic_vector(15 downto 0);
 
 
 
  --alu signals
 
 
 
  signal AluOp: std_logic_vector(4 downto 0);
 
 
 
  signal AluIn1: std_logic_vector(7 downto 0);
 
 
 
  signal AluIn2: std_logic_vector(7 downto 0);
 
 
 
  signal AluOut: std_logic_vector(7 downto 0);
 
 
 
  signal TR: std_logic;
 
 
 
 
 
  --control signals
 
  --control signals
 
  signal InReset: std_logic;
 
  signal InReset: std_logic;
 
 
 
  signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
 
 
 
  signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
 
 
 
  signal OpWW: std_logic;
 
 
 
  signal OpWE: std_logic;
 
 
 
 
 
  --opcode shortcut signals
 
  --opcode shortcut signals
 
  signal opmain: std_logic_vector(3 downto 0);
 
  signal opmain: std_logic_vector(3 downto 0);
 
  signal opimmd: std_logic_vector(7 downto 0);
 
  signal opimmd: std_logic_vector(7 downto 0);
 
  signal opcond1: std_logic; --first conditional bit
 
  signal opcond1: std_logic; --first conditional bit
Line 118... Line 131... 
  signal opreg1: std_logic_vector(2 downto 0);
 
  signal opreg1: std_logic_vector(2 downto 0);
 
  signal opreg2: std_logic_vector(2 downto 0);
 
  signal opreg2: std_logic_vector(2 downto 0);
 
  signal opreg3: std_logic_vector(2 downto 0);
 
  signal opreg3: std_logic_vector(2 downto 0);
 
  signal opseges: std_logic; --use ES segment
 
  signal opseges: std_logic; --use ES segment
 
 
 
 
 
 
 
  signal regbank: std_logic;
 
 
 
 
 
  signal fetcheraddress: std_logic_vector(15 downto 0);
 
  signal fetcheraddress: std_logic_vector(15 downto 0);
 
 
 
 
 
 
 
  --temporary signals
 
 
 
  signal tempreg1: std_logic_vector(3 downto 0);
 
 
 
  signal tempreg2: std_logic_vector(3 downto 0);
 
 
 
  signal tempreg3: std_logic_vector(3 downto 0);
 
 
 
  signal FetchMemAddr: std_logic_vector(15 downto 0);
 
 
 
 
 
 
 
 
 
begin
 
begin
 
  reg: registerfile port map(
 
  reg: registerfile port map(
 
    WriteEnable => regWE,
 
    WriteEnable => regWE,
 
    DataIn => regIn,
 
    DataIn => regIn,
 
    Clock => Clock,
 
    Clock => Clock,
Line 135... Line 158... 
    Addend => IPAddend,
 
    Addend => IPAddend,
 
    DataOut => IPCarryOut,
 
    DataOut => IPCarryOut,
 
    SegmentOut => CSCarryOut,
 
    SegmentOut => CSCarryOut,
 
    Clock => Clock
 
    Clock => Clock
 
  );
 
  );
 
 
 
  carryoverss: carryover port map(
 
 
 
    EnableCarry => CarrySS,
 
 
 
    DataIn => regIn(REGSP),
 
 
 
    SegmentIn => RegIn(REGSS),
 
 
 
    Addend => SPAddend,
 
 
 
    DataOut => SPCarryOut,
 
 
 
    SegmentOut => SSCarryOut,
 
 
 
    Clock => Clock
 
 
 
  );
 
  fetcher: fetch port map(
 
  fetcher: fetch port map(
 
    Enable => fetchEN,
 
    Enable => fetchEN,
 
    AddressIn => fetcheraddress,
 
    AddressIn => fetcheraddress,
 
    Clock => Clock,
 
    Clock => Clock,
 
    DataIn => MemIn,
 
    DataIn => MemIn,
 
    IROut => IR,
 
    IROut => IR,
 
    AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
 
    AddressOut => FetchMemAddr
 
 
 
  );
 
 
 
  cpualu: alu port map(
 
 
 
    Op => AluOp,
 
 
 
    DataIn1 => AluIn1,
 
 
 
    DataIn2 => AluIn2,
 
 
 
    DataOut => AluOut,
 
 
 
    TR => TR
 
  );
 
  );
 
  fetcheraddress <= regIn(REGCS) & regIn(REGIP);
 
  fetcheraddress <= regIn(REGCS) & regIn(REGIP);
 
 
 
  MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
 
 
 
  MemOut <= OpData when (state=WaitForMemory and OpWE='1') else x"0000";
 
 
 
  MemWE <= OpWE when state=WaitForMemory else '0';
 
 
 
  MemWW <= OpWW when state=WaitForMemory else '0';
 
 
 
  OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
 
  --opcode shortcuts
 
  --opcode shortcuts
 
  opmain <= IR(15 downto 12);
 
  opmain <= IR(15 downto 12);
 
  opimmd <= IR(7 downto 0);
 
  opimmd <= IR(7 downto 0);
 
  opcond1 <= IR(8);
 
  opcond1 <= IR(8);
 
  opcond2 <= IR(7);
 
  opcond2 <= IR(7);
Line 160... Line 202... 
  --debug ports
 
  --debug ports
 
  DebugCS <= regOut(REGCS);
 
  DebugCS <= regOut(REGCS);
 
  DebugIP <= regOut(REGIP);
 
  DebugIP <= regOut(REGIP);
 
  DebugR0 <= regOut(0);
 
  DebugR0 <= regOut(0);
 
  DebugIR <= IR;
 
  DebugIR <= IR;
 
 
 
  DebugTR <= TR;
 
 
 
  --register addresses with registerbank baked in
 
 
 
  tempreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
 
 
 
  tempreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
 
 
 
  tempreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
 
 
 
 
 
 
 
 
 
 
 
 
 
  decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
 
  decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
 
  begin
 
  begin
Line 178... Line 225... 
        CarrySS <= '0';
 
        CarrySS <= '0';
 
        regWE <= (others => '1');
 
        regWE <= (others => '1');
 
        regIn <= (others => "00000000");
 
        regIn <= (others => "00000000");
 
        regIn(REGCS) <= x"01";
 
        regIn(REGCS) <= x"01";
 
        IPAddend <= x"00";
 
        IPAddend <= x"00";
 
 
 
        SPAddend <= x"00";
 
 
 
        AluOp <= "10001"; --reset TR in ALU
 
 
 
        regbank <= '0';
 
        fetchEN <= '1';
 
        fetchEN <= '1';
 
 
 
        OpData <= "ZZZZZZZZZZZZZZZZ";
 
 
 
        OpAddress <= x"0000";
 
 
 
        OpWE <= '0';
 
 
 
        opWW <= '0';
 
        --finish up
 
        --finish up
 
      elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
 
      elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
 
        InReset <= '0';
 
        InReset <= '0';
 
        fetchEN <= '1';
 
        fetchEN <= '1';
 
        state <= FirstFetch1;
 
        state <= FirstFetch1;
Line 217... Line 271... 
      elsif state=FirstFetch2 then
 
      elsif state=FirstFetch2 then
 
        state <= FirstFetch3;
 
        state <= FirstFetch3;
 
 
 
 
 
      elsif state=FirstFetch3 then
 
      elsif state=FirstFetch3 then
 
        state <= Execute;
 
        state <= Execute;
 
 
 
      elsif state=WaitForMemory then
 
 
 
        state <= Execute;
 
 
 
        FetchEn <= '1';
 
 
 
        IpAddend <= x"02";
 
      end if;
 
      end if;
 
 
 
 
 
 
 
 
 
      if state=Execute then
 
      if state=Execute then
 
        fetchEN <= '1';
 
        fetchEN <= '1';
Line 230... Line 288... 
        RegWE <= (others => '0');
 
        RegWE <= (others => '0');
 
        regIn(REGIP) <= IPCarryOut;
 
        regIn(REGIP) <= IPCarryOut;
 
        regWE(REGIP) <= '1';
 
        regWE(REGIP) <= '1';
 
        regWE(REGCS) <= '1';
 
        regWE(REGCS) <= '1';
 
        regIn(REGCS) <= CSCarryOut;
 
        regIn(REGCS) <= CSCarryOut;
 
 
 
        regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
 
        MemWE <= '0';
 
        regIn(REGSS) <= SSCarryOut;
 
        MemWW <= '0';
 
        regWE(REGSP) <= '1';
 
 
 
        regWE(REGSS) <= '1';
 
 
 
        OpAddress <= "ZZZZZZZZZZZZZZZZ";
 
 
 
 
 
        --actual decoding
 
        --actual decoding
 
 
 
        if opcond1='0' or (opcond1='1' and TR='1') then
 
        case opmain is
 
        case opmain is
 
          when "0000" => --mov reg,imm
 
          when "0000" => --mov reg,imm
 
            --if to_integer(unsigned(opreg1)) = REGIP then
 
              regIn(to_integer(unsigned(tempreg1))) <= opimmd;
 
 
 
              regWE(to_integer(unsigned(tempreg1))) <= '1';
 
            RegIn(to_integer(unsigned(opreg1))) <= opimmd;
 
            when "0001" => --mov [reg],imm
 
            RegWE(to_integer(unsigned(opreg1))) <= '1';
 
              OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(tempreg1)));
 
 
 
              OpWE <= '1';
 
 
 
              OpData <= x"00" & opimmd;
 
 
 
              OpWW <= '0';
 
 
 
              state <= WaitForMemory;
 
 
 
              IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
 
 
 
              FetchEN <= '0';
 
          when others =>
 
          when others =>
 
            --synthesis off
 
            --synthesis off
 
            report "Not implemented" severity error;
 
            report "Not implemented" severity error;
 
            --synthesis on
 
            --synthesis on
 
        end case;
 
        end case;
 
      end if;
 
      end if;
 
 
 
      end if;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    end if;
 
    end if;

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