| Line 151... |
Line 151... |
Clock => Clock,
|
Clock => Clock,
|
DataOut => regOut
|
DataOut => regOut
|
);
|
);
|
carryovercs: carryover port map(
|
carryovercs: carryover port map(
|
EnableCarry => CarryCS,
|
EnableCarry => CarryCS,
|
DataIn => regIn(REGIP),
|
DataIn => regOut(REGIP),
|
SegmentIn => regIn(REGCS),
|
SegmentIn => regOut(REGCS),
|
Addend => IPAddend,
|
Addend => IPAddend,
|
DataOut => IPCarryOut,
|
DataOut => IPCarryOut,
|
SegmentOut => CSCarryOut,
|
SegmentOut => CSCarryOut,
|
Clock => Clock
|
Clock => Clock
|
);
|
);
|
carryoverss: carryover port map(
|
carryoverss: carryover port map(
|
EnableCarry => CarrySS,
|
EnableCarry => CarrySS,
|
DataIn => regIn(REGSP),
|
DataIn => regOut(REGSP),
|
SegmentIn => RegIn(REGSS),
|
SegmentIn => RegOut(REGSS),
|
Addend => SPAddend,
|
Addend => SPAddend,
|
DataOut => SPCarryOut,
|
DataOut => SPCarryOut,
|
SegmentOut => SSCarryOut,
|
SegmentOut => SSCarryOut,
|
Clock => Clock
|
Clock => Clock
|
);
|
);
|
| Line 184... |
Line 184... |
DataOut => AluOut,
|
DataOut => AluOut,
|
TR => TR
|
TR => TR
|
);
|
);
|
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
|
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
|
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else x"0000";
|
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
|
MemWE <= OpWE when state=WaitForMemory else '0';
|
MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
|
MemWW <= OpWW when state=WaitForMemory else '0';
|
MemWW <= OpWW when state=WaitForMemory else 'Z' when state=HoldMEmory else '0';
|
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
|
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
|
--opcode shortcuts
|
--opcode shortcuts
|
opmain <= IR(15 downto 12);
|
opmain <= IR(15 downto 12);
|
opimmd <= IR(7 downto 0);
|
opimmd <= IR(7 downto 0);
|
opcond1 <= IR(8);
|
opcond1 <= IR(8);
|
| Line 243... |
Line 243... |
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
state <= HoldMemory;
|
state <= HoldMemory;
|
HoldAck <= '1';
|
HoldAck <= '1';
|
FetchEN <= '0';
|
FetchEN <= '0';
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
|
MemWE <= 'Z';
|
|
MemWW <= 'Z';
|
|
elsif Hold='0' and state=HoldMemory then
|
elsif Hold='0' and state=HoldMemory then
|
if reset='1' or InReset='1' then
|
if reset='1' or InReset='1' then
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
else
|
else
|
state <= Execute;
|
state <= Execute;
|
