| Line 14... |
Line 14... |
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteEnable: in std_logic;
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WriteEnable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0);
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Port0: inout std_logic_vector(7 downto 0)
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-- Reset: in std_logic
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-- Reset: in std_logic
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--RAM/ROM interface (RAMA is built in to here
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--RAM/ROM interface (RAMA is built in to here
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--RAMBDataIn: out std_logic_vector(15 downto 0);
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--RAMBDataIn: out std_logic_vector(15 downto 0);
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--RAMBDataOut: in std_logic_vector(15 downto 0);
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--RAMBDataOut: in std_logic_vector(15 downto 0);
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| Line 38... |
Line 40... |
DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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|
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constant R1START: integer := 0;
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constant R1START: integer := 15;
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constant R1END: integer := 1023;
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constant R1END: integer := 1023+15;
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signal addr: std_logic_vector(15 downto 0) := (others => '0');
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signal addr: std_logic_vector(15 downto 0) := (others => '0');
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signal R1addr: std_logic_vector(7 downto 0);
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signal R1addr: std_logic_vector(7 downto 0);
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signal we: std_logic_vector(1 downto 0);
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signal we: std_logic_vector(1 downto 0);
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signal datawrite: std_logic_vector(15 downto 0);
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signal datawrite: std_logic_vector(15 downto 0);
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signal dataread: std_logic_vector(15 downto 0);
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signal dataread: std_logic_vector(15 downto 0);
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--signal en: std_logic;
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--signal en: std_logic;
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signal R1we: std_logic_vector(1 downto 0);
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signal R1we: std_logic_vector(1 downto 0);
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signal R1en: std_logic;
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signal R1en: std_logic;
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signal R1in: std_logic_vector(15 downto 0);
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signal R1in: std_logic_vector(15 downto 0);
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signal R1out: std_logic_vector(15 downto 0);
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signal R1out: std_logic_vector(15 downto 0);
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|
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signal port0we: std_logic_vector(7 downto 0);
|
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signal port0temp: std_logic_vector(7 downto 0);
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begin
|
begin
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R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
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R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
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addrwe: process(Address, WriteWord, WriteEnable, DataIn)
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addrwe: process(Address, WriteWord, WriteEnable, DataIn)
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begin
|
begin
|
addr <= Address(15 downto 1) & '0';
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addr <= Address(15 downto 1) & '0';
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| Line 74... |
Line 79... |
datawrite <= x"0000";
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datawrite <= x"0000";
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we <= "00";
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we <= "00";
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end if;
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end if;
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end process;
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end process;
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|
|
assignram: process (we, datawrite, addr, r1out)
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assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address)
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variable tmp: integer;
|
variable tmp: integer;
|
|
variable tmp2: integer;
|
variable found: boolean := false;
|
variable found: boolean := false;
|
begin
|
begin
|
tmp := to_integer(unsigned(addr));
|
tmp := to_integer(unsigned(addr));
|
if tmp >= R1START and tmp <= R1END then
|
tmp2 := to_integer(unsigned(Address));
|
|
if tmp2 <= 15 then --internal registers/mapped IO
|
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if WriteWord='0' then
|
|
if tmp2=0 then
|
|
dataread <= x"0000";
|
|
gen: for I in 0 to 7 loop
|
|
if WriteEnable='1' then
|
|
if port0we(I)='1' then --1-bit port set to WRITE mode
|
|
port0(I) <= DataIn(I);
|
|
port0temp(I) <= DataIn(I);
|
|
else
|
|
port0(I) <= 'Z';
|
|
end if;
|
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else --not WE
|
|
if port0we(I)='0' then --1-bit-port set to READ mode
|
|
dataread(I) <= port0(I);
|
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else
|
|
dataread(I) <= port0temp(I);
|
|
end if;
|
|
end if;
|
|
end loop gen;
|
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elsif tmp2=1 then
|
|
dataread <= x"00" & port0we;
|
|
if WriteEnable='1' then
|
|
port0we <= DataIn(7 downto 0);
|
|
setwe: for I in 0 to 7 loop
|
|
if DataIn(I)='0' then
|
|
port0(I) <= 'Z';
|
|
end if;
|
|
end loop setwe;
|
|
else
|
|
dataread <= x"00" & port0we;
|
|
end if;
|
|
else
|
|
--synthesis off
|
|
report "Memory address is outside of bounds of RAM and registers" severity warning;
|
|
--synthesis on
|
|
end if;
|
|
else
|
|
--synthesis off
|
|
report "WriteWord is not allowed in register area. Ignoring access" severity warning;
|
|
--synthesis on
|
|
end if;
|
|
elsif tmp >= R1START and tmp <= R1END then --RAM bank1
|
--map all to R1
|
--map all to R1
|
found := true;
|
found := true;
|
R1en <= '1';
|
R1en <= '1';
|
R1we <= we;
|
R1we <= we;
|
R1in <= datawrite;
|
R1in <= datawrite;
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| Line 104... |
Line 153... |
DataOut <= dataread;
|
DataOut <= dataread;
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else
|
else
|
DataOut <= x"00" & dataread(15 downto 8);
|
DataOut <= x"00" & dataread(15 downto 8);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
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No newline at end of file
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No newline at end of file
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