| Line 17... |
Line 17... |
Clock: in std_logic;
|
Clock: in std_logic;
|
DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
|
DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
|
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
|
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
|
WriteEnable: in std_logic;
|
WriteEnable: in std_logic;
|
Data: inout std_logic_vector(15 downto 0);
|
Data: inout std_logic_vector(15 downto 0);
|
|
Port0: inout std_logic_vector(7 downto 0);
|
--debug ports
|
--debug ports
|
DebugR0: out std_logic_vector(7 downto 0)
|
DebugR0: out std_logic_vector(7 downto 0)
|
);
|
);
|
end top;
|
end top;
|
|
|
| Line 31... |
Line 32... |
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
|
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
|
WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
|
WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
|
WriteEnable: in std_logic;
|
WriteEnable: in std_logic;
|
Clock: in std_logic;
|
Clock: in std_logic;
|
DataIn: in std_logic_vector(15 downto 0);
|
DataIn: in std_logic_vector(15 downto 0);
|
DataOut: out std_logic_vector(15 downto 0)
|
DataOut: out std_logic_vector(15 downto 0);
|
|
Port0: inout std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component core is
|
component core is
|
port(
|
port(
|
| Line 97... |
Line 99... |
Address => MemAddress,
|
Address => MemAddress,
|
WriteWord => MemWriteWord,
|
WriteWord => MemWriteWord,
|
WriteEnable => MemWriteEnable,
|
WriteEnable => MemWriteEnable,
|
Clock => Clock,
|
Clock => Clock,
|
DataIn => MemDataIn,
|
DataIn => MemDataIn,
|
DataOut => MemDataOut
|
DataOut => MemDataOut,
|
|
Port0 => Port0
|
);
|
);
|
|
|
MemAddress <= cpuaddr when DMA='0' else Address;
|
MemAddress <= cpuaddr when DMA='0' else Address;
|
MemWriteWord <= cpuww when DMA='0' else '1';
|
MemWriteWord <= cpuww when DMA='0' else '1';
|
MemWriteEnable <= cpuwe when DMA='0' else WriteEnable;
|
MemWriteEnable <= cpuwe when DMA='0' else WriteEnable;
|
