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https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
[/] [tinycpu/] [trunk/] [testbench/] [core_tb.vhd] - Diff between revs 33 and 34
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| Rev 33 |
Rev 34 |
| Line 175... |
Line 175... |
wait for 10 ns;
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wait for 10 ns;
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MemIn <= x"0020"; --the value to be popped into r0
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MemIn <= x"0020"; --the value to be popped into r0
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assert(MemAddr=x"0200") report "Pop is not fetching from correct address" severity error;
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assert(MemAddr=x"0200") report "Pop is not fetching from correct address" severity error;
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wait for 10 ns;
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wait for 10 ns;
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assert(DebugR0=x"20") report "Pop is not assigning to R0 correct" severity error;
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assert(DebugR0=x"20") report "Pop is not assigning to R0 correct" severity error;
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MemIn <= x"0040";
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MemIn <= x"0040"; --mov r0, 0x40
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wait for 10 ns;
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wait for 10 ns;
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MemIn <= b"0101_0010_0000_0001"; --mov r1,r0
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wait for 10 ns;
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MemIn <= b"0101_0000_0001_0010"; --mov r0, [r1]
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wait for 10 ns;
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assert(MemAddr=x"0040") report "load operation doesn't fetch from proper address" severity error;
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MemIn <= x"1234"; --value to be loaded to r0 (lower value only)
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wait for 10 ns;
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assert(DebugR0=x"34") report "load operation doesn't load into r0 properly" severity error;
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MemIn <= b"0101_0000_0001_0011"; --mov [r0], r1
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wait for 10 ns;
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assert(MemAddr=x"0034") report "store operation doesn't store to proper address" severity error;
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assert(MemOut=x"0040") report "store operation doesn't have proper value" severity error;
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wait for 10 ns;
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MemIn <= x"0010";
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-- summary of testbench
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-- summary of testbench
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assert false
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assert false
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report "Testbench of core completed successfully!"
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report "Testbench of core completed successfully!"
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severity note;
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severity note;
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