| Line 17... |
Line 17... |
Clock: in std_logic;
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Clock: in std_logic;
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DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
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DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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WriteEnable: in std_logic;
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WriteEnable: in std_logic;
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Data: inout std_logic_vector(15 downto 0);
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Data: inout std_logic_vector(15 downto 0);
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Port0: inout std_logic_vector(7 downto 0);
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--debug ports
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--debug ports
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DebugR0: out std_logic_vector(7 downto 0)
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DebugR0: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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| Line 30... |
Line 31... |
signal HoldAck: std_logic;
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signal HoldAck: std_logic;
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signal DMA: std_logic:='0'; --when high, Address, WriteEnable, and Data are connected to memory
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signal DMA: std_logic:='0'; --when high, Address, WriteEnable, and Data are connected to memory
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signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes)
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signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes)
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signal WriteEnable: std_logic:='0';
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signal WriteEnable: std_logic:='0';
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signal Data: std_logic_vector(15 downto 0):=x"0000";
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signal Data: std_logic_vector(15 downto 0):=x"0000";
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signal Port0: std_logic_vector(7 downto 0);
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--debug ports
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--debug ports
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signal DebugR0: std_logic_vector(7 downto 0);
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signal DebugR0: std_logic_vector(7 downto 0);
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|
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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| Line 48... |
Line 50... |
Clock => Clock,
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Clock => Clock,
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DMA => DMA,
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DMA => DMA,
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Address => Address,
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Address => Address,
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WriteEnable => WriteEnable,
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WriteEnable => WriteEnable,
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Data => Data,
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Data => Data,
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DebugR0 => DebugR0
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DebugR0 => DebugR0,
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Port0 => Port0
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);
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);
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|
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
|
