URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_debug_if.v] - Diff between revs 49 and 55

Rev 49	Rev 55
Line 52...	Line 52...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/12/04 21:14:16 gorban`
	`// committed the debug interface file`
	`//`

	`// synopsys translate_off`
	`include "timescale.v"
	`// synopsys translate_on`

	`include "uart_defines.v"

`module uart_debug_if (/AUTOARG/`	`module uart_debug_if (/AUTOARG/`
`// Outputs`	`// Outputs`
`wb_dat32_o,`	`wb_dat32_o,`
`// Inputs`	`// Inputs`
Line 92...	Line 101...
`// 5 + 2 + 5 + 4 + 5 + 3`	`// 5 + 2 + 5 + 4 + 5 + 3`
`5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};`	`5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};`
`default: wb_dat32_o = 0;`	`default: wb_dat32_o = 0;`
`endcase // case(wb_adr_i)`	`endcase // case(wb_adr_i)`

`endmodule`	`endmodule // uart_debug_if`


`No newline at end of file`	`No newline at end of file`