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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_defines.v] - Diff between revs 29 and 45
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| Rev 29 |
Rev 45 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2001/08/24 21:01:12 mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.6 2001/08/23 16:05:05 mohor
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// Revision 1.6 2001/08/23 16:05:05 mohor
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// Stop bit bug fixed.
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// Stop bit bug fixed.
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// Parity bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// OE indicator (Overrun Error) bug fixed.
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Line 173... |
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_POINTER_W 4
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`define UART_FIFO_POINTER_W 4
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`define UART_FIFO_COUNTER_W 5
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`define UART_FIFO_COUNTER_W 5
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// receiver fifo has width 10 because it has parity and framing error bits
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// receiver fifo has width 11 because it has break, parity and framing error bits
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`define UART_FIFO_REC_WIDTH 10
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`define UART_FIFO_REC_WIDTH 11
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