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Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.8 2001/11/26 21:38:54 gorban
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// Revision 1.8 2001/11/26 21:38:54 gorban
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// Lots of fixes:
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// Lots of fixes:
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// Break condition wasn't handled correctly at all.
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// Break condition wasn't handled correctly at all.
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// LSR bits could lose their values.
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// LSR bits could lose their values.
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// LSR value after reset was wrong.
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// LSR value after reset was wrong.
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`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
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`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
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`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
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`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
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`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
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`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
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`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
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`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
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`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
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`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
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`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
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`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
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`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
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`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
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`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
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// Interrupt Enable register bits
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// Interrupt Enable register bits
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`define UART_IE_RDA 0 // Received Data available interrupt
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`define UART_IE_RDA 0 // Received Data available interrupt
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