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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_defines.v] - Diff between revs 75 and 79

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Rev 75 Rev 79
Line 112... Line 112...
// remove comments to restore use to the old version with 8 data bit interface
// remove comments to restore use to the old version with 8 data bit interface
// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
// also, in 8-bit version there'll be no debugging features included
// also, in 8-bit version there'll be no debugging features included
// `define DATA_BUS_WIDTH_8
// `define DATA_BUS_WIDTH_8
 
 
`define BIG_BYTE_ENDIAN     // Defines endian
 
 
 
`ifdef DATA_BUS_WIDTH_8
`ifdef DATA_BUS_WIDTH_8
 `define UART_ADDR_WIDTH 3
 `define UART_ADDR_WIDTH 3
 `define UART_DATA_WIDTH 8
 `define UART_DATA_WIDTH 8
`else
`else
 `define UART_ADDR_WIDTH 5
 `define UART_ADDR_WIDTH 5
 `define UART_DATA_WIDTH 32
 `define UART_DATA_WIDTH 32
`endif
`endif
 
 
 
// Uncomment this if you want your UART to have 
 
// 16xBaudrate output port.
 
// If defined, the enable signal will be used to drive baudrate_o signal
 
// It's frequency is 16xbaudrate
 
 
 
// `define UART_HAS_BAUDRATE_OUTPUT
 
 
// Register addresses
// Register addresses
`define UART_REG_RB     `UART_ADDR_WIDTH'd0     // receiver buffer
`define UART_REG_RB     `UART_ADDR_WIDTH'd0     // receiver buffer
`define UART_REG_TR  `UART_ADDR_WIDTH'd0        // transmitter
`define UART_REG_TR  `UART_ADDR_WIDTH'd0        // transmitter
`define UART_REG_IE     `UART_ADDR_WIDTH'd1     // Interrupt enable
`define UART_REG_IE     `UART_ADDR_WIDTH'd1     // Interrupt enable
`define UART_REG_II  `UART_ADDR_WIDTH'd2        // Interrupt identification
`define UART_REG_II  `UART_ADDR_WIDTH'd2        // Interrupt identification

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