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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_defines.v] - Diff between revs 87 and 89

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Rev 87 Rev 89
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.13  2003/06/11 16:37:47  gorban
 
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
 
//
// Revision 1.12  2002/07/22 23:02:23  gorban
// Revision 1.12  2002/07/22 23:02:23  gorban
// Bug Fixes:
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
// Initial revision
//
//
//
//
 
 
// remove comments to restore use to the old version with 8 data bit interface
// remove comments to restore to use the new version with 8 data bit interface
// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
// also, in 8-bit version there'll be no debugging features included
// also, in 8-bit version there'll be no debugging features included
`define DATA_BUS_WIDTH_8
// CAUTION: doesn't work with current version of OR1200
 
//`define DATA_BUS_WIDTH_8
 
 
`ifdef DATA_BUS_WIDTH_8
`ifdef DATA_BUS_WIDTH_8
 `define UART_ADDR_WIDTH 3
 `define UART_ADDR_WIDTH 3
 `define UART_DATA_WIDTH 8
 `define UART_DATA_WIDTH 8
`else
`else

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