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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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//
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// Revision 1.23 2001/12/19 07:33:54 mohor
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// Revision 1.23 2001/12/19 07:33:54 mohor
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// Synplicity was having troubles with the comment.
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// Synplicity was having troubles with the comment.
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//
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//
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// Revision 1.22 2001/12/17 14:46:48 mohor
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// Revision 1.22 2001/12/17 14:46:48 mohor
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// overrun signal was moved to separate block because many sequential lsr
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// overrun signal was moved to separate block because many sequential lsr
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// synopsys translate_on
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// synopsys translate_on
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`include "uart_defines.v"
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`include "uart_defines.v"
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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input clk;
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input clk;
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input wb_rst_i;
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input wb_rst_i;
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input [7:0] lcr;
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input [7:0] lcr;
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input rf_pop;
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input rf_pop;
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output [`UART_FIFO_COUNTER_W-1:0] rf_count;
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output [`UART_FIFO_COUNTER_W-1:0] rf_count;
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output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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output rf_overrun;
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output rf_overrun;
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output rf_error_bit;
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output rf_error_bit;
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output [3:0] rstate;
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output [3:0] rstate;
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output rf_push;
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output rf_push_pulse;
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reg [3:0] rstate;
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reg [3:0] rstate;
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reg [3:0] rcounter16;
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reg [3:0] rcounter16;
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reg [2:0] rbit_counter;
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reg [2:0] rbit_counter;
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reg [7:0] rshift; // receiver shift register
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reg [7:0] rshift; // receiver shift register
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reg [7:0] counter_b; // counts the 0 (low) signals
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reg [7:0] counter_b; // counts the 0 (low) signals
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// RX FIFO signals
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// RX FIFO signals
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reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
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reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
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wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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wire rf_push_pulse;
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reg rf_push;
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reg rf_push;
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wire rf_pop;
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wire rf_pop;
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wire rf_overrun;
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wire rf_overrun;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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uart_fifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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uart_fifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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.clk( clk ),
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.wb_rst_i( wb_rst_i ),
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.data_in( rf_data_in ),
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.data_in( rf_data_in ),
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.data_out( rf_data_out ),
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.data_out( rf_data_out ),
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.push( rf_push ),
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.push( rf_push_pulse ),
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.pop( rf_pop ),
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.pop( rf_pop ),
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.overrun( rf_overrun ),
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.overrun( rf_overrun ),
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.count( rf_count ),
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.count( rf_count ),
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.error_bit( rf_error_bit ),
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.error_bit( rf_error_bit ),
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.fifo_reset( rx_reset ),
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.fifo_reset( rx_reset ),
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default : rstate <= #1 sr_idle;
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default : rstate <= #1 sr_idle;
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endcase
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endcase
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end // if (enable)
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end // if (enable)
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end // always of receiver
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end // always of receiver
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always @ (posedge clk or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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rf_push_q <= 0;
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else
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rf_push_q <= #1 rf_push;
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end
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assign rf_push_pulse = rf_push & ~rf_push_q;
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//
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//
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// Break condition detection.
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// Break condition detection.
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// Works in conjuction with the receiver state machine
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// Works in conjuction with the receiver state machine
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reg [9:0] toc_value; // value to be set to timeout counter
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reg [9:0] toc_value; // value to be set to timeout counter
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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counter_t <= #1 10'd639; // 10 bits for the default 8N1
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counter_t <= #1 10'd639; // 10 bits for the default 8N1
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else
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else
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if(rf_push || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
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if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
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counter_t <= #1 toc_value;
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counter_t <= #1 toc_value;
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else
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else
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if (enable && counter_t != 10'b0) // we don't want to underflow
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if (enable && counter_t != 10'b0) // we don't want to underflow
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counter_t <= #1 counter_t - 1;
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counter_t <= #1 counter_t - 1;
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end
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end
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