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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2001/12/30 20:39:13 mohor
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// More than one character was stored in case of break. End of the break
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// was not detected correctly.
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//
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// Revision 1.26 2001/12/20 13:28:27 mohor
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// Revision 1.26 2001/12/20 13:28:27 mohor
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// Missing declaration of rf_push_q fixed.
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// Missing declaration of rf_push_q fixed.
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//
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//
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// Revision 1.25 2001/12/20 13:25:46 mohor
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// Revision 1.25 2001/12/20 13:25:46 mohor
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// rx push changed to be only one cycle wide.
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// rx push changed to be only one cycle wide.
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Line 172... |
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "uart_defines.v"
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//`include "uart_defines.v"
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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input clk;
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input clk;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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wire break_error = (counter_b == 0);
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wire break_error = (counter_b == 0);
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// RX FIFO instance
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// RX FIFO instance
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uart_fifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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.clk( clk ),
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.wb_rst_i( wb_rst_i ),
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.data_in( rf_data_in ),
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.data_in( rf_data_in ),
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.data_out( rf_data_out ),
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.data_out( rf_data_out ),
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.push( rf_push_pulse ),
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.push( rf_push_pulse ),
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parameter sr_rec_prepare = 4'd6;
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parameter sr_rec_prepare = 4'd6;
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parameter sr_end_bit = 4'd7;
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parameter sr_end_bit = 4'd7;
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parameter sr_ca_lc_parity = 4'd8;
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parameter sr_ca_lc_parity = 4'd8;
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parameter sr_wait1 = 4'd9;
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parameter sr_wait1 = 4'd9;
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parameter sr_push = 4'd10;
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parameter sr_push = 4'd10;
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parameter sr_last = 4'd11;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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begin
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case (rstate)
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case (rstate)
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sr_idle : begin
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sr_idle : begin
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rf_push <= #1 1'b0;
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rf_push <= #1 1'b0;
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rf_data_in <= #1 0;
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rf_data_in <= #1 0;
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rcounter16 <= #1 4'b1110;
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if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
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if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
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begin
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begin
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rstate <= #1 sr_rec_start;
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rstate <= #1 sr_rec_start;
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rcounter16 <= #1 4'b1110;
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end
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end
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end
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end
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sr_rec_start : begin
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sr_rec_start : begin
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if (rcounter16_eq_7) // check the pulse
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if (rcounter16_eq_7) // check the pulse
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if (srx_pad_i==1'b1) // no start bit
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if (srx_pad_i==1'b1) // no start bit
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if(break_error)
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if(break_error)
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rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
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rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
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else
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else
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rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
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rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
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rf_push <= #1 1'b1;
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rf_push <= #1 1'b1;
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rstate <= #1 sr_last;
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rstate <= #1 sr_idle;
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end
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end
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end
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end
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sr_last : begin
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if (rcounter16_eq_1 & srx_pad_i | break_error)
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rstate <= #1 sr_idle;
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rcounter16 <= #1 rcounter16_minus_1;
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rf_push <= #1 1'b0;
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end
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default : rstate <= #1 sr_idle;
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default : rstate <= #1 sr_idle;
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endcase
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endcase
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end // if (enable)
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end // if (enable)
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end // always of receiver
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end // always of receiver
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