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[/ ] [uart16550/ ] [trunk/ ] [rtl/ ] [verilog/ ] [uart_regs.v ] - Diff between revs 99 and 105
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////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
// //
// CVS Revision History // CVS Revision History
// //
// $Log: not supported by cvs2svn $ // $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban // Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
// //
// Revision 1.39 2002/07/29 21:16:18 gorban // Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources. // The uart_defines.v file is included again in sources.
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assign rls_int = ier[ `UART_IE_RLS] && ( lsr[ `UART_LS_OE] || lsr[ `UART_LS_PE] || lsr[ `UART_LS_FE] || lsr[ `UART_LS_BI] ) ; assign rls_int = ier[ `UART_IE_RLS] && ( lsr[ `UART_LS_OE] || lsr[ `UART_LS_PE] || lsr[ `UART_LS_FE] || lsr[ `UART_LS_BI] ) ;
assign rda_int = ier[ `UART_IE_RDA] && ( rf_count >= { 1 'b0, trigger_level} ) ; assign rda_int = ier[ `UART_IE_RDA] && ( rf_count >= { 1 'b0, trigger_level} ) ;
assign thre_int = ier[ `UART_IE_THRE] && lsr[ `UART_LS_TFE] ; assign thre_int = ier[ `UART_IE_THRE] && lsr[ `UART_LS_TFE] ;
assign ms_int = ier[ `UART_IE_MS] && ( | msr[ 3 : 0 ] ) ; assign ms_int = ier[ `UART_IE_MS] && ( | msr[ 3 : 0 ] ) ;
assign ti_int = ier[ `UART_IE_RDA] && ( counter_t == 1 0 'b0) ; assign ti_int = ier[ `UART_IE_RDA] && ( counter_t == 1 0 'b0) && ( | rf_count) ;
reg rls_int_d; reg rls_int_d;
reg thre_int_d; reg thre_int_d;
reg ms_int_d; reg ms_int_d;
reg ti_int_d; reg ti_int_d;
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