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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.25 2001/11/28 19:36:39 gorban
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// Revision 1.25 2001/11/28 19:36:39 gorban
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// Fixed: timeout and break didn't pay attention to current data format when counting time
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// Fixed: timeout and break didn't pay attention to current data format when counting time
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//
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//
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// Revision 1.24 2001/11/26 21:38:54 gorban
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// Revision 1.24 2001/11/26 21:38:54 gorban
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// Lots of fixes:
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// Lots of fixes:
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Line 295... |
// Transmitter Instance
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// Transmitter Instance
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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// Receiver Instance
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// Receiver Instance
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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always @(/*AUTOSENSE*/dl or dlab or ier or iir
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always @(/*AUTOSENSE*/dl or dlab or ier or iir
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or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
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or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
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Line 371... |
else
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else
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if (msr_read)
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if (msr_read)
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msi_reset <= #1 1; // reset bits in Modem Status Register
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msi_reset <= #1 1; // reset bits in Modem Status Register
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end
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end
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/*
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// threi_clear signal handling
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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threi_clear <= #1 0;
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else
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if (!lsr[`UART_LS_TFE] && (tf_count==0)) // reset clear flag when tx fifo clears
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threi_clear <= #1 0;
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else
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if (wb_re_i && wb_addr_i == `UART_REG_II)
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threi_clear <= #1 1;
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end
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*/
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//
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//
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// WRITES AND RESETS //
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// WRITES AND RESETS //
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//
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//
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// Line Control Register
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// Line Control Register
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Line 479... |
end
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end
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// Line Status Register
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// Line Status Register
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// activation conditions
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// activation conditions
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assign lsr0 = (rf_count==0 && fifo_write); // data in receiver fifo available set condition
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assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
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assign lsr1 = rf_overrun; // Receiver overrun error
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assign lsr1 = rf_overrun; // Receiver overrun error
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr5 = (tf_count==5'b0); // transmitter fifo is empty
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assign lsr5 = (tf_count==5'b0); // transmitter fifo is empty
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if (wb_rst_i) lsr4r <= #1 0;
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if (wb_rst_i) lsr4r <= #1 0;
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else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
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else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
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// lsr bit 5 (transmitter fifo is empty)
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// lsr bit 5 (transmitter fifo is empty)
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reg lsr5_d;
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reg lsr5_d;
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wire tx_fifo_write;
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assign tx_fifo_write = (wb_we_i && ~dlab && wb_addr_i==`UART_REG_TR);
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i) lsr5_d <= #1 1;
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if (wb_rst_i) lsr5_d <= #1 1;
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else lsr5_d <= #1 lsr5;
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else lsr5_d <= #1 lsr5;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i) lsr5r <= #1 1;
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if (wb_rst_i) lsr5r <= #1 1;
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else lsr5r <= #1 (tx_fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
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else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
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// lsr bit 6 (transmitter empty indicator)
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// lsr bit 6 (transmitter empty indicator)
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reg lsr6_d;
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reg lsr6_d;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i) lsr6_d <= #1 1;
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if (wb_rst_i) lsr6_d <= #1 1;
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else lsr6_d <= #1 lsr6;
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else lsr6_d <= #1 lsr6;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i) lsr6r <= #1 1;
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if (wb_rst_i) lsr6r <= #1 1;
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else lsr6r <= #1 (tx_fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
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else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
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// lsr bit 7 (error in fifo)
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// lsr bit 7 (error in fifo)
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reg lsr7_d;
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reg lsr7_d;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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