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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.37 2001/12/27 13:24:09 mohor
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// lsr[7] was not showing overrun errors.
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//
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// Revision 1.36 2001/12/20 13:25:46 mohor
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// Revision 1.36 2001/12/20 13:25:46 mohor
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// rx push changed to be only one cycle wide.
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// rx push changed to be only one cycle wide.
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//
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//
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// Revision 1.35 2001/12/19 08:03:34 mohor
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// Revision 1.35 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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// Warnings cleared.
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Line 196... |
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "uart_defines.v"
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//`include "uart_defines.v"
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`define UART_DL1 7:0
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`define UART_DL1 7:0
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`define UART_DL2 15:8
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`define UART_DL2 15:8
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module uart_regs (clk,
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module uart_regs (clk,
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`else
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`else
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// debug interface signals enabled
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// debug interface signals enabled
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ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
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ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
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`endif
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`endif
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rts_pad_o, dtr_pad_o, int_o
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rts_pad_o, dtr_pad_o, int_o
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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, baud_o
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`endif
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);
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);
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input clk;
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input clk;
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input wb_rst_i;
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input wb_rst_i;
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input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
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input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
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input [3:0] modem_inputs;
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input [3:0] modem_inputs;
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output rts_pad_o;
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output rts_pad_o;
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output dtr_pad_o;
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output dtr_pad_o;
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output int_o;
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output int_o;
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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output baud_o;
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`endif
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`ifdef DATA_BUS_WIDTH_8
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`ifdef DATA_BUS_WIDTH_8
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`else
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`else
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// if 32-bit databus and debug interface are enabled
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// if 32-bit databus and debug interface are enabled
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output [3:0] ier;
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output [3:0] ier;
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`endif
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`endif
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wire [3:0] modem_inputs;
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wire [3:0] modem_inputs;
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reg enable;
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reg enable;
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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assign baud_o = enable; // baud_o is actually the enable signal
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`endif
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wire stx_pad_o; // received from transmitter module
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wire stx_pad_o; // received from transmitter module
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wire srx_pad_i;
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wire srx_pad_i;
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reg [7:0] wb_dat_o;
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reg [7:0] wb_dat_o;
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wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
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wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
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reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
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reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
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reg [7:0] block_value; // One character length minus stop bit
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reg [7:0] block_value; // One character length minus stop bit
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// Transmitter Instance
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// Transmitter Instance
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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wire serial_out;
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
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// handle loopback
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wire serial_in = loopback ? serial_out : srx_pad_i;
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assign stx_pad_o = loopback ? 1'b1 : serial_out;
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// Receiver Instance
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// Receiver Instance
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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always @(dl or dlab or ier or iir or scratch
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always @(dl or dlab or ier or iir or scratch
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