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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.39 2002/07/29 21:16:18 gorban
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// The uart_defines.v file is included again in sources.
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//
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// Revision 1.38 2002/07/22 23:02:23 gorban
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// Revision 1.38 2002/07/22 23:02:23 gorban
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// Bug Fixes:
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// Bug Fixes:
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// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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// Problem reported by Kenny.Tung.
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// Problem reported by Kenny.Tung.
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// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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if (wb_rst_i) lsr0_d <= #1 0;
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if (wb_rst_i) lsr0_d <= #1 0;
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else lsr0_d <= #1 lsr0;
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else lsr0_d <= #1 lsr0;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i) lsr0r <= #1 0;
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if (wb_rst_i) lsr0r <= #1 0;
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else lsr0r <= #1 (rf_count==1 && fifo_read || rx_reset) ? 0 : // deassert condition
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else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
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lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
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lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
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// lsr bit 1 (receiver overrun)
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// lsr bit 1 (receiver overrun)
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reg lsr1_d; // delayed
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reg lsr1_d; // delayed
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