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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Diff between revs 87 and 99

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.40  2003/06/11 16:37:47  gorban
 
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
 
//
// Revision 1.39  2002/07/29 21:16:18  gorban
// Revision 1.39  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
// The uart_defines.v file is included again in sources.
//
//
// Revision 1.38  2002/07/22 23:02:23  gorban
// Revision 1.38  2002/07/22 23:02:23  gorban
// Bug Fixes:
// Bug Fixes:
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`endif
`endif
 
 
 
 
wire                                                                            stx_pad_o;              // received from transmitter module
wire                                                                            stx_pad_o;              // received from transmitter module
wire                                                                            srx_pad_i;
wire                                                                            srx_pad_i;
 
wire                                                                            srx_pad;
 
 
reg [7:0]                                                                wb_dat_o;
reg [7:0]                                                                wb_dat_o;
 
 
wire [`UART_ADDR_WIDTH-1:0]              wb_addr_i;
wire [`UART_ADDR_WIDTH-1:0]              wb_addr_i;
wire [7:0]                                                               wb_dat_i;
wire [7:0]                                                               wb_dat_i;
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// Transmitter Instance
// Transmitter Instance
wire serial_out;
wire serial_out;
 
 
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
 
 
 
  // Synchronizing and sampling serial RX input
 
  uart_sync_flops    i_uart_sync_flops
 
  (
 
    .rst_i           (wb_rst_i),
 
    .clk_i           (clk),
 
    .stage1_rst_i    (1'b0),
 
    .stage1_clk_en_i (1'b1),
 
    .async_dat_i     (srx_pad_i),
 
    .sync_dat_o      (srx_pad)
 
  );
 
  defparam i_uart_sync_flops.width      = 1;
 
  defparam i_uart_sync_flops.init_value = 1'b1;
 
 
// handle loopback
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad_i;
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
 
 
// Receiver Instance
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);

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