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https://opencores.org/ocsvn/uart16550/uart16550/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2001/12/06 14:51:04 gorban
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// Bug in LSR[0] is fixed.
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// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
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//
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// Revision 1.15 2001/12/03 21:44:29 gorban
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// Revision 1.15 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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`else
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`else
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uart_debug_if dbg(/*AUTOINST*/
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uart_debug_if dbg(/*AUTOINST*/
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// Outputs
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// Outputs
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.wb_dat32_o (wb_dat32_o[31:0]),
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.wb_dat32_o (wb_dat32_o[31:0]),
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// Inputs
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// Inputs
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
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.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
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.re_o (re_o),
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.ier (ier[3:0]),
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.ier (ier[3:0]),
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.iir (iir[3:0]),
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.iir (iir[3:0]),
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.fcr (fcr[1:0]),
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.fcr (fcr[1:0]),
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.mcr (mcr[4:0]),
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.mcr (mcr[4:0]),
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.lcr (lcr[7:0]),
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.lcr (lcr[7:0]),
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