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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2001/11/08 14:54:23 mohor
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// Comments in Slovene language deleted, few small fixes for better work of
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// old tools. IRQs need to be fix.
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//
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// Revision 1.12 2001/11/07 17:51:52 gorban
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// Revision 1.12 2001/11/07 17:51:52 gorban
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// Heavily rewritten interrupt and LSR subsystems.
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// Heavily rewritten interrupt and LSR subsystems.
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// Many bugs hopefully squashed.
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// Many bugs hopefully squashed.
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//
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//
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// Revision 1.11 2001/10/29 17:00:46 gorban
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// Revision 1.11 2001/10/29 17:00:46 gorban
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "uart_defines.v"
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`include "uart_defines.v"
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module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset, lsr_mask);
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module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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input clk;
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input clk;
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input wb_rst_i;
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input wb_rst_i;
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input [7:0] lcr;
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input [7:0] lcr;
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input tf_push;
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input tf_push;
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input [7:0] wb_dat_i;
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input [7:0] wb_dat_i;
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input enable;
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input enable;
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input tx_reset;
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input tx_reset;
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input lsr_mask; //reset of fifo
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input lsr_mask; //reset of fifo
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output stx_pad_o;
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output stx_pad_o;
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output [2:0] state;
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output [2:0] tstate;
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output [`UART_FIFO_COUNTER_W-1:0] tf_count;
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output [`UART_FIFO_COUNTER_W-1:0] tf_count;
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reg [2:0] state;
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reg [2:0] tstate;
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reg [4:0] counter;
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reg [4:0] counter;
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reg [2:0] bit_counter; // counts the bits to be sent
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reg [2:0] bit_counter; // counts the bits to be sent
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reg [6:0] shift_out; // output shift register
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reg [6:0] shift_out; // output shift register
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reg stx_o_tmp;
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reg stx_o_tmp;
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reg parity_xor; // parity of the word
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reg parity_xor; // parity of the word
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| Line 175... |
Line 179... |
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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begin
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state <= #1 s_idle;
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tstate <= #1 s_idle;
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stx_o_tmp <= #1 1'b1;
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stx_o_tmp <= #1 1'b1;
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counter <= #1 5'b0;
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counter <= #1 5'b0;
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shift_out <= #1 7'b0;
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shift_out <= #1 7'b0;
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bit_out <= #1 1'b0;
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bit_out <= #1 1'b0;
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parity_xor <= #1 1'b0;
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parity_xor <= #1 1'b0;
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Line 191... |
bit_counter <= #1 3'b0;
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bit_counter <= #1 3'b0;
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end
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end
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else
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else
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if (enable)
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if (enable)
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begin
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begin
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case (state)
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case (tstate)
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s_idle : if (~|tf_count) // if tf_count==0
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s_idle : if (~|tf_count) // if tf_count==0
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begin
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begin
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state <= #1 s_idle;
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tstate <= #1 s_idle;
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stx_o_tmp <= #1 1'b1;
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stx_o_tmp <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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tf_pop <= #1 1'b0;
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tf_pop <= #1 1'b0;
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stx_o_tmp <= #1 1'b1;
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stx_o_tmp <= #1 1'b1;
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state <= #1 s_pop_byte;
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tstate <= #1 s_pop_byte;
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end
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end
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s_pop_byte : begin
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s_pop_byte : begin
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tf_pop <= #1 1'b1;
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tf_pop <= #1 1'b1;
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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2'b00 : begin
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2'b00 : begin
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bit_counter <= #1 3'b111;
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bit_counter <= #1 3'b111;
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parity_xor <= #1 ^tf_data_out[7:0];
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parity_xor <= #1 ^tf_data_out[7:0];
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end
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end
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endcase
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endcase
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{shift_out[6:0], bit_out} <= #1 tf_data_out;
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{shift_out[6:0], bit_out} <= #1 tf_data_out;
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state <= #1 s_send_start;
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tstate <= #1 s_send_start;
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end
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end
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s_send_start : begin
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s_send_start : begin
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tf_pop <= #1 1'b0;
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tf_pop <= #1 1'b0;
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if (~|counter)
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if (~|counter)
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counter <= #1 5'b01111;
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counter <= #1 5'b01111;
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else
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else
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if (counter == 5'b00001)
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if (counter == 5'b00001)
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begin
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begin
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counter <= #1 0;
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counter <= #1 0;
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state <= #1 s_send_byte;
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tstate <= #1 s_send_byte;
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end
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end
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else
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else
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counter <= #1 counter - 1'b1;
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counter <= #1 counter - 1'b1;
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stx_o_tmp <= #1 1'b0;
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stx_o_tmp <= #1 1'b0;
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end
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end
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begin
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begin
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if (bit_counter > 3'b0)
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if (bit_counter > 3'b0)
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begin
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begin
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bit_counter <= #1 bit_counter - 1'b1;
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bit_counter <= #1 bit_counter - 1'b1;
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{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};
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{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};
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state <= #1 s_send_byte;
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tstate <= #1 s_send_byte;
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end
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end
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else // end of byte
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else // end of byte
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if (~lcr[`UART_LC_PE])
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if (~lcr[`UART_LC_PE])
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begin
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begin
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state <= #1 s_send_stop;
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tstate <= #1 s_send_stop;
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end
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end
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else
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else
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begin
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begin
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case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
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case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
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2'b00: bit_out <= #1 ~parity_xor;
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2'b00: bit_out <= #1 ~parity_xor;
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2'b01: bit_out <= #1 1'b1;
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2'b01: bit_out <= #1 1'b1;
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2'b10: bit_out <= #1 parity_xor;
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2'b10: bit_out <= #1 parity_xor;
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2'b11: bit_out <= #1 1'b0;
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2'b11: bit_out <= #1 1'b0;
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endcase
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endcase
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state <= #1 s_send_parity;
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tstate <= #1 s_send_parity;
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end
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end
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counter <= #1 0;
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counter <= #1 0;
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end
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end
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else
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else
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counter <= #1 counter - 1'b1;
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counter <= #1 counter - 1'b1;
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counter <= #1 5'b01111;
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counter <= #1 5'b01111;
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else
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else
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if (counter == 5'b00001)
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if (counter == 5'b00001)
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begin
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begin
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counter <= #1 4'b0;
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counter <= #1 4'b0;
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state <= #1 s_send_stop;
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tstate <= #1 s_send_stop;
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end
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end
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else
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else
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counter <= #1 counter - 1'b1;
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counter <= #1 counter - 1'b1;
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stx_o_tmp <= #1 bit_out;
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stx_o_tmp <= #1 bit_out;
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end
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end
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if (~|counter)
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if (~|counter)
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begin
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begin
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casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
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casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
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3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor
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3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor
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3'b100: counter <= #1 5'b10101; // 1.5 stop bit
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3'b100: counter <= #1 5'b10101; // 1.5 stop bit
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3'b1xx: counter <= #1 5'b11101; // 2 stop bits
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default: counter <= #1 5'b11101; // 2 stop bits
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endcase
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endcase
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end
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end
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else
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else
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if (counter == 5'b00001)
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if (counter == 5'b00001)
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begin
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begin
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counter <= #1 0;
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counter <= #1 0;
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state <= #1 s_idle;
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tstate <= #1 s_idle;
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end
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end
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else
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else
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counter <= #1 counter - 1'b1;
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counter <= #1 counter - 1'b1;
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stx_o_tmp <= #1 1'b1;
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stx_o_tmp <= #1 1'b1;
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end
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end
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default : // should never get here
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default : // should never get here
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state <= #1 s_idle;
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tstate <= #1 s_idle;
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endcase
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endcase
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end // end if enable
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end // end if enable
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end // transmitter logic
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end // transmitter logic
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assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
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assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
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