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Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2002/01/08 11:29:40 mohor
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// tf_pop was too wide. Now it is only 1 clk cycle width.
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//
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// Revision 1.15 2001/12/17 14:46:48 mohor
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// Revision 1.15 2001/12/17 14:46:48 mohor
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// overrun signal was moved to separate block because many sequential lsr
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// overrun signal was moved to separate block because many sequential lsr
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// reads were preventing data from being written to rx fifo.
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// reads were preventing data from being written to rx fifo.
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// underrun signal was not used and was removed from the project.
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// underrun signal was not used and was removed from the project.
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//
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//
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//
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//
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// Transmitter FIFO signals
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// Transmitter FIFO signals
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wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
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wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
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wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
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wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
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wire tf_push;
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wire tf_push;
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wire tf_overrun;
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//wire tf_overrun;
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wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
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wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
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assign tf_data_in = wb_dat_i;
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assign tf_data_in = wb_dat_i;
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uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO
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uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO
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Line 171... |
Line 174... |
.wb_rst_i( wb_rst_i ),
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.wb_rst_i( wb_rst_i ),
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.data_in( tf_data_in ),
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.data_in( tf_data_in ),
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.data_out( tf_data_out ),
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.data_out( tf_data_out ),
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.push( tf_push ),
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.push( tf_push ),
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.pop( tf_pop ),
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.pop( tf_pop ),
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.overrun( tf_overrun ),
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.overrun( /*tf_overrun*/ ),
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.count( tf_count ),
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.count( tf_count ),
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.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor
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.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor
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.fifo_reset( tx_reset ),
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.fifo_reset( tx_reset ),
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.reset_status(lsr_mask)
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.reset_status(lsr_mask)
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);
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);
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