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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Diff between revs 70 and 74

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Rev 70 Rev 74
Line 61... Line 61...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.16  2002/01/08 11:29:40  mohor
 
// tf_pop was too wide. Now it is only 1 clk cycle width.
 
//
// Revision 1.15  2001/12/17 14:46:48  mohor
// Revision 1.15  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
// underrun signal was not used and was removed from the project.
//
//
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//
//
// Transmitter FIFO signals
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
wire                                                                                    tf_push;
wire                                                                                    tf_push;
wire                                                                                    tf_overrun;
//wire                                                                                  tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
 
 
assign                                                                          tf_data_in = wb_dat_i;
assign                                                                          tf_data_in = wb_dat_i;
 
 
uart_fifo fifo_tx(      // error bit signal is not used in transmitter FIFO
uart_fifo fifo_tx(      // error bit signal is not used in transmitter FIFO
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        .wb_rst_i(      wb_rst_i        ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .pop(           tf_pop          ),
        .overrun(       tf_overrun      ),
        .overrun(       /*tf_overrun*/  ),
        .count(         tf_count        ),
        .count(         tf_count        ),
        .error_bit(),                 // Ta ni priklopljen. Prej je manjkal, dodal Igor
        .error_bit(),                 // Ta ni priklopljen. Prej je manjkal, dodal Igor
        .fifo_reset(    tx_reset        ),
        .fifo_reset(    tx_reset        ),
        .reset_status(lsr_mask)
        .reset_status(lsr_mask)
);
);

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