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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// uart_TX_FIFO.v ////
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//// uart_wb.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// ////
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| Line 62... |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2001/08/24 21:01:12 mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.7 2001/08/23 16:05:05 mohor
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// Revision 1.7 2001/08/23 16:05:05 mohor
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// Stop bit bug fixed.
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// Stop bit bug fixed.
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// Parity bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// OE indicator (Overrun Error) bug fixed.
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| Line 90... |
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//
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//
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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// Company: Flextronics Semiconductor
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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module uart_wb (clk,
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module uart_wb (clk,
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wb_rst_i,
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wb_rst_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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we_o, re_o // Write and read enable output for the core
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we_o, re_o // Write and read enable output for the core
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