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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2002/02/07 16:20:20 gorban
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// major bug in 32-bit mode that prevented register access fixed.
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//
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// Revision 1.12 2001/12/19 08:03:34 mohor
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// Revision 1.12 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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// Warnings cleared.
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//
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//
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// Revision 1.11 2001/12/06 14:51:04 gorban
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// Revision 1.11 2001/12/06 14:51:04 gorban
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// Bug in LSR[0] is fixed.
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// Bug in LSR[0] is fixed.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "uart_defines.v"
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//`include "uart_defines.v"
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module uart_wb (clk, wb_rst_i,
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module uart_wb (clk, wb_rst_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
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wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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we_o, re_o // Write and read enable output for the core
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we_o, re_o // Write and read enable output for the core
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wb_stb_is <= #1 wb_stb_i;
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wb_stb_is <= #1 wb_stb_i;
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wb_dat_is <= #1 wb_dat_i;
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wb_dat_is <= #1 wb_dat_i;
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wb_sel_is <= #1 wb_sel_i;
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wb_sel_is <= #1 wb_sel_i;
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end
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end
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assign wb_adr_int = wb_adr_is;
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`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
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`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 0;
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wb_dat_o <= #1 0;
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else
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else
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wb_dat_o <= #1 wb_dat8_o;
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wb_dat_o <= #1 wb_dat8_o;
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always @(wb_dat_is)
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always @(wb_dat_is)
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wb_dat8_i = wb_dat_is;
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wb_dat8_i = wb_dat_is;
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assign wb_adr_int = wb_adr_is;
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`else // 32-bit bus
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`else // 32-bit bus
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// put output to the correct byte in 32 bits using select line
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// put output to the correct byte in 32 bits using select line
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 0;
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wb_dat_o <= #1 0;
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4'b0100 : wb_dat8_i = wb_dat_is[23:16];
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4'b0100 : wb_dat8_i = wb_dat_is[23:16];
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4'b1000 : wb_dat8_i = wb_dat_is[31:24];
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4'b1000 : wb_dat8_i = wb_dat_is[31:24];
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default : wb_dat8_i = wb_dat_is[7:0];
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default : wb_dat8_i = wb_dat_is[7:0];
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endcase // case(wb_sel_i)
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endcase // case(wb_sel_i)
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reg [1:0] adr2 ; // lower 2 bits of regenerated address
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always @(wb_sel_is)
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case (wb_sel_is)
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`ifdef BIG_BYTE_ENDIAN
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4'b0001 : adr2 = 2'b11;
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4'b0010 : adr2 = 2'b10;
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4'b0100 : adr2 = 2'b01;
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4'b1000 : adr2 = 2'b00;
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`else
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4'b0001 : adr2 = 2'b00;
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4'b0010 : adr2 = 2'b01;
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4'b0100 : adr2 = 2'b10;
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4'b1000 : adr2 = 2'b11;
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`endif
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default : adr2 = 2'b0;
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endcase // case(wb_sel_is)
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assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], adr2};
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`endif // !`ifdef DATA_BUS_WIDTH_8
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`endif // !`ifdef DATA_BUS_WIDTH_8
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endmodule
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endmodule
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