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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2002/07/22 23:02:23 gorban
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// Bug Fixes:
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// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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// Problem reported by Kenny.Tung.
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// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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// * Made FIFO's as general inferrable memory where possible.
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// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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// * Added optional baudrate output (baud_o).
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// This is identical to BAUDOUT* signal on 16550 chip.
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// It outputs 16xbit_clock_rate - the divided clock.
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// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.12 2001/12/19 08:03:34 mohor
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// Revision 1.12 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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// Warnings cleared.
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//
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//
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// Revision 1.11 2001/12/06 14:51:04 gorban
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// Revision 1.11 2001/12/06 14:51:04 gorban
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// Bug in LSR[0] is fixed.
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// Bug in LSR[0] is fixed.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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//`include "uart_defines.v"
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`include "uart_defines.v"
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module uart_wb (clk, wb_rst_i,
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module uart_wb (clk, wb_rst_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
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wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
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we_o, re_o // Write and read enable output for the core
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we_o, re_o // Write and read enable output for the core
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