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Line 1... |
--
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--
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-- UART receiver
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-- UART receiver
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 27.01.2008
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-- Date: 27.01.2008
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-- Version: 1.1
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-- Version: 1.2
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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| Line 60... |
Line 60... |
CLEAR : in std_logic; -- Reset process
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CLEAR : in std_logic; -- Reset process
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D : in std_logic; -- Signal input
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal D was at least THRESHOLD samples high
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Q : out std_logic -- Signal D was at least THRESHOLD samples high
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);
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);
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end component;
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end component;
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component slib_input_filter is
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generic (
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SIZE : natural := 4 -- Filter counter size
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);
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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CE : in std_logic; -- Clock enable
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal output
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);
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end component;
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-- Counter
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-- Counter
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component slib_counter is
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component slib_counter is
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generic (
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generic (
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WIDTH : natural := 4 -- Counter width
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WIDTH : natural := 4 -- Counter width
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);
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);
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Line 96... |
-- FSM
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-- FSM
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type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
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type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
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signal CState, NState : state_type;
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signal CState, NState : state_type;
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-- Signals
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-- Signals
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signal iBaudCount : std_logic_vector(3 downto 0); -- Baud counter output
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signal iBaudCountClear : std_logic; -- Baud counter clear
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signal iBaudCountClear : std_logic; -- Baud counter clear
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signal iBaudStep : std_logic; -- Next symbol pulse
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signal iBaudStep : std_logic; -- Next symbol pulse
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signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
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signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
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signal iFilterClear : std_logic; -- Reset input filter
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signal iFilterClear : std_logic; -- Reset input filter
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signal iFSIN : std_logic; -- Filtered SIN
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signal iFSIN : std_logic; -- Filtered SIN
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signal iFStopBit : std_logic; -- Filtered SIN for stop bit detection
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signal iParity : std_logic; -- Data parity
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signal iParity : std_logic; -- Data parity
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signal iParityReceived : std_logic; -- Parity received
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signal iParityReceived : std_logic; -- Parity received
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signal iDataCount : integer range 0 to 8; -- Data bit counter
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signal iDataCount : integer range 0 to 8; -- Data bit counter
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signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
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signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
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signal iDataCountFinish : std_logic; -- Data bit counter finished
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signal iDataCountFinish : std_logic; -- Data bit counter finished
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Line 127... |
CLEAR => iBaudCountClear,
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CLEAR => iBaudCountClear,
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LOAD => '0',
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LOAD => '0',
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ENABLE => RXCLK,
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ENABLE => RXCLK,
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DOWN => '0',
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DOWN => '0',
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D => x"0",
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D => x"0",
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Q => iBaudCount,
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OVERFLOW => iBaudStep
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OVERFLOW => iBaudStep
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);
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);
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-- Input filter
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-- Input filter
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RX_MVF: slib_mv_filter generic map (
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RX_MVF: slib_mv_filter generic map (
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| Line 128... |
Line 144... |
CLEAR => iFilterClear,
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CLEAR => iFilterClear,
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D => SIN,
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D => SIN,
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Q => iFSIN
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Q => iFSIN
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);
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);
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-- Input filter for the stop bit
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RX_IFSB: slib_input_filter generic map (
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SIZE => 4
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) port map (
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CLK => CLK,
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RST => RST,
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CE => RXCLK,
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D => SIN,
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Q => iFStopBit
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);
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-- iBaudStepD
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-- iBaudStepD
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RX_IFC: process (CLK, RST)
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RX_IFC: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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iBaudStepD <= '0';
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iBaudStepD <= '0';
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| Line 181... |
Line 208... |
CState <= NState;
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CState <= NState;
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end if;
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end if;
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end process;
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end process;
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-- RX FSM
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-- RX FSM
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RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
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RX_FSM: process (CState, SIN, iFSIN, iFStopBit, iBaudStep, iBaudCount, iDataCountFinish, PEN, WLS, STB)
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begin
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begin
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-- Defaults
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-- Defaults
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NState <= IDLE;
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NState <= IDLE;
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iBaudCountClear <= '0';
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iBaudCountClear <= '0';
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iDataCountInit <= '0';
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iDataCountInit <= '0';
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| Line 217... |
Line 244... |
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
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when PAR => if (iBaudStep = '1') then -- Wait for parity bit
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NState <= STOP;
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NState <= STOP;
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else
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else
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NState <= PAR;
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NState <= PAR;
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end if;
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end if;
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when STOP => if (iBaudStep = '1') then -- Wait for stop bit
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when STOP => if (iBaudCount(3) = '1') then -- Wait for stop bit
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if (iFSIN = '0') then -- No stop bit received
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if (iFStopBit = '0') then -- No stop bit received
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iRXFinished <= '1';
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iRXFinished <= '1';
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NState <= MWAIT;
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NState <= MWAIT;
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else
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else
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iRXFinished <= '1';
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iRXFinished <= '1';
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NState <= IDLE; -- Stop bit end
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NState <= IDLE; -- Stop bit end
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| Line 266... |
Line 293... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Framing error and break interrupt
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-- Framing error and break interrupt
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iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
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iNoStopReceived <= '1' when iFStopBit = '0' and (CState = STOP) else '0';
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iBI <= '1' when iDOUT = "00000000" and
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iBI <= '1' when iDOUT = "00000000" and
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iParityReceived = '0' and
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iParityReceived = '0' and
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iNoStopReceived = '1' else '0';
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iNoStopReceived = '1' else '0';
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iFE <= '1' when iNoStopReceived = '1' else '0';
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iFE <= '1' when iNoStopReceived = '1' else '0';
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