URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Diff between revs 17 and 23

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Rev 17	Rev 23
Line 5...	Line 5...
`# Programs`	`# Programs`
`GHDL = ghdl`	`GHDL = ghdl`
`PERL = perl`	`PERL = perl`

`# Directories`	`# Directories`
`SRCDIR = vhdl`	`SRCDIR = ../../../rtl/vhdl`
`TBDIR = tbench`	`TBDIR = ../../../bench/vhdl`
`SIMDIR = sim`	`SIMDIR = ../bin`
	`LOGDIR = ../log`

`# UART16750 sources`	`# UART16750 sources`
`SRC = slib_clock_div.vhd`	`SRC = slib_clock_div.vhd`
`SRC += slib_counter.vhd`	`SRC += slib_counter.vhd`
`SRC += slib_edge_detect.vhd`	`SRC += slib_edge_detect.vhd`
Line 30...	Line 31...
`TBSRC += uart_package.vhd`	`TBSRC += uart_package.vhd`
`TBSRC += uart_transactor.vhd`	`TBSRC += uart_transactor.vhd`

`# Testbench stimuli and log`	`# Testbench stimuli and log`
`TBSTIMGEN = $(SIMDIR)/uart_test_stim.pl`	`TBSTIMGEN = $(SIMDIR)/uart_test_stim.pl`
`TBSTIMDAT = $(SIMDIR)/uart_stim.dat`	`TBSTIMDAT = uart_stim.dat`
`TBLOG = $(SIMDIR)/uart_log.txt`	`TBLOG = $(LOGDIR)/uart_log.txt`
`TBVCD = $(SIMDIR)/uart_log.vcd`	`TBVCD = $(LOGDIR)/uart_log.vcd`

`# Simulation entity and options`	`# Simulation entity and options`
`SIMPROG = uart_transactor`	`SIMPROG = uart_transactor`
`SIMOPTS = --stop-time=140ms`	`SIMOPTS = --stop-time=160ms`

`all: $(SIMPROG)`	`all: $(SIMPROG)`

`$(TBSTIMDAT): $(TBSTIMGEN)`	`$(TBSTIMDAT): $(TBSTIMGEN)`
`$(PERL) $^ > $@`	`$(PERL) $^ > $@`
Line 49...	Line 50...
`$(GHDL) -a $^`	`$(GHDL) -a $^`
`$(GHDL) -e $@`	`$(GHDL) -e $@`

`sim: $(SIMPROG) $(TBSTIMDAT)`	`sim: $(SIMPROG) $(TBSTIMDAT)`
`$(GHDL) -r $(SIMPROG) $(SIMOPTS)`	`$(GHDL) -r $(SIMPROG) $(SIMOPTS)`
	`cp uart_log.txt $(TBLOG)`

`vcd: $(SIMPROG) $(TBSTIMDAT)`	`vcd: $(SIMPROG) $(TBSTIMDAT)`
`$(GHDL) -r $(SIMPROG) $(SIMOPTS) --vcd=$(TBVCD)`	`$(GHDL) -r $(SIMPROG) $(SIMOPTS) --vcd=$(TBVCD)`

`clean:`	`clean:`

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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Diff between revs 17 and 23