| Line 59... |
Line 59... |
variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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wait_clk_cycles := (others => '0');
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wait_clk_cycles := (others => '0');
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-- Divide cycle_wait by 4
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-- Divide cycle_wait by 8
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--cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
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--cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
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--cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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--cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2); -- Shift right by 2
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--cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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cycle_wait_oversample := "000" & cycle_wait(cycle_wait'high downto 3); -- Shift right by 3
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-- Half of cycle_wait_oversample
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-- Half of cycle_wait_oversample
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half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); -- Shift right by 1
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half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); -- Shift right by 1
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genTickOverSample <= '0';
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genTickOverSample <= '0';
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| Line 84... |
Line 85... |
end if;
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end if;
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end if;
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end if;
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-- Avoid creation of transparent latch (By default the VHDL will create an register for vectors that are assigned only in one
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-- Avoid creation of transparent latch (By default the VHDL will create an register for vectors that are assigned only in one
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-- ocasion of a (if, case) instruction
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-- ocasion of a (if, case) instruction
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cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2);
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cycle_wait_oversample := "000" & cycle_wait(cycle_wait'high downto 3);
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half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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