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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [uart_wishbone_slave.vhd] - Diff between revs 14 and 21
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Rev 21 |
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0);
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0);
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WE_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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ACK_O : out STD_LOGIC;
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serial_in : in std_logic;
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serial_in : in std_logic;
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data_Avaible : out std_logic; -- Indicate that the receiver module got something
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serial_out : out std_logic
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serial_out : out std_logic
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);
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);
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end uart_wishbone_slave;
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end uart_wishbone_slave;
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architecture Behavioral of uart_wishbone_slave is
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architecture Behavioral of uart_wishbone_slave is
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serial_out => serial_out,
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serial_out => serial_out,
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serial_in => serial_in,
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serial_in => serial_in,
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start_tx => tx_start
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start_tx => tx_start
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);
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);
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data_Avaible <= rx_data_ready;
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end Behavioral;
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end Behavioral;
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