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https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk
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| Line 118... |
Line 118... |
//start bit
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//start bit
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uart_.txd = 0;
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uart_.txd = 0;
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#(1/baud_rate)s;
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#(1/baud_rate)s;
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//8 bits of data
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//8 bits of data
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for(uint8 i=0; i<8; i++) begin
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for(uint8 i=0; i<8; i++) begin
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uart_.txd = data_bits[7-i];
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uart_.txd = data_bits[i]; //least significant bit first.
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#(1/baud_rate)s;
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#(1/baud_rate)s;
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end
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end
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//1 stop bit
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//1 stop bit
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uart_.txd = 1;
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uart_.txd = 1;
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#(1/baud_rate)s;
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#(1/baud_rate)s;
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| Line 152... |
Line 152... |
//Look for a valid start bit. Must be at least 1/2 bit period duration.
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//Look for a valid start bit. Must be at least 1/2 bit period duration.
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@(negedge uart_.rxd);
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@(negedge uart_.rxd);
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#(0.5 * 1/baud_rate)s;
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#(0.5 * 1/baud_rate)s;
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if ( uart_.rxd == 0 ) begin
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if ( uart_.rxd == 0 ) begin
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logic[7:0] data_bits;
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logic[7:0] data_bits;
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uint32 bit_count = 7;
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//read in 8 data bits, LSBit first, sampling in the center of the bit period.
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//read in 8 data bits, MSBit first, sampling in the center of the bit period.
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for(uint8 i=0; i<8; i++) begin
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repeat(8) begin
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#( 1/baud_rate )s;
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#( 1/baud_rate )s;
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data_bits[ bit_count-- ] = uart_.rxd;
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data_bits[i] = uart_.rxd;
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end
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end
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//check stop bit.
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//check stop bit.
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#( 1/baud_rate )s;
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#( 1/baud_rate )s;
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if ( uart_.rxd != 1 ) begin
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if ( uart_.rxd != 1 ) begin
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$display("Monitor: Invalid stop bit.");
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$display("Monitor: Invalid stop bit.");
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