| Line 7... |
Line 7... |
---- ----
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---- ----
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---- Description ----
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---- Description ----
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-- Serial UART with byte wide register interface for control/status, data, and baud rate.
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-- Serial UART with byte wide register interface for control/status, data, and baud rate.
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-- Transmit(Tx) and Receive(Rx) data is FIFO buffered. Tx and Rx FIFO size configurable independently.
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-- Transmit(Tx) and Receive(Rx) data is FIFO buffered. Tx and Rx FIFO size configurable independently.
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-- Currently only supports no parity, 8 data bits, 1 stop bit (N81).
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-- Currently only supports no parity, 8 data bits, 1 stop bit (N81).
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-- Data is sent most significant bit first.
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-- Data is sent least significant bit first.
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-- Baud rate divisor set via 16 bit register, allowing a wide range of baud rates and system clocks.
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-- Baud rate divisor set via 16 bit register, allowing a wide range of baud rates and system clocks.
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--
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--
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-- Future:
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-- Future:
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-- - insertion and checking of parity bit
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-- - insertion and checking of parity bit
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-- - data bit order configurable
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-- - data bit order configurable
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| Line 257... |
Line 257... |
--output 1 start bit
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--output 1 start bit
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when START =>
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when START =>
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if tx_bit_enable then
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if tx_bit_enable then
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txd := '0';
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txd := '0';
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tx_state := DATA;
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tx_state := DATA;
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tx_data_count := 7;
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tx_data_count := 0;
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end if;
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end if;
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--output 8 data bits
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--output 8 data bits, least significant bit first.
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when DATA =>
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when DATA =>
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if tx_bit_enable then
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if tx_bit_enable then
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txd := tx_fifo_read_data(tx_data_count);
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txd := tx_fifo_read_data(tx_data_count);
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if tx_data_count = 0 then
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if tx_data_count = 7 then
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tx_state := STOP;
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tx_state := STOP;
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else
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else
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tx_data_count := tx_data_count - 1;
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tx_data_count := tx_data_count + 1;
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end if;
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end if;
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end if;
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end if;
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--output 1 stop bit
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--output 1 stop bit
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when STOP =>
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when STOP =>
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if tx_bit_enable then
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if tx_bit_enable then
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| Line 304... |
Line 304... |
if rxd /= '0' then
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if rxd /= '0' then
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--start bit has not stayed low for longer than 1/2 a bit period.
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--start bit has not stayed low for longer than 1/2 a bit period.
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rx_state := IDLE;
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rx_state := IDLE;
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elsif rx_bit_enable then
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elsif rx_bit_enable then
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rx_state := DATA;
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rx_state := DATA;
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rx_data_count := 7;
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rx_data_count := 0;
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end if;
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end if;
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--read in 8 data bits.
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--read in 8 data bits.
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when DATA =>
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when DATA =>
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if rx_bit_enable then
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if rx_bit_enable then
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rx_fifo_write_data(rx_data_count) <= rxd;
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rx_fifo_write_data(rx_data_count) <= rxd;
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if rx_data_count = 0 then
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if rx_data_count = 7 then
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rx_state := STOP;
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rx_state := STOP;
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else
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else
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rx_data_count := rx_data_count - 1;
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rx_data_count := rx_data_count + 1;
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end if;
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end if;
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end if;
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end if;
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--check stop bit is '1'. If not, set the rx error flag.
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--check stop bit is '1'. If not, set the rx error flag.
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when STOP =>
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when STOP =>
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if rx_bit_enable then
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if rx_bit_enable then
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