URL https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk

Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] [rtl/] [uart.vhd] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 96...	Line 96...
`reset : in std_logic; --synchronous reset`	`reset : in std_logic; --synchronous reset`
`--Serial UART`	`--Serial UART`
`i_rxd : in std_logic; --receive serial data (asynchronous)`	`i_rxd : in std_logic; --receive serial data (asynchronous)`
`o_txd : out std_logic; --transmit serial data`	`o_txd : out std_logic; --transmit serial data`
`--Cpu register interface`	`--Cpu register interface`
`i_addr : in std_logic_vector(15 downto 0); --highest index is msb of address.`	`i_addr : in std_logic_vector; --highest index is msb of address.`
`i_write_enable : in std_logic; --high for 1 clk period for a write`	`i_write_enable : in std_logic; --high for 1 clk period for a write`
`i_read_enable : in std_logic; --high for 1 clk period for a read`	`i_read_enable : in std_logic; --high for 1 clk period for a read`
`i_data : in std_logic_vector(7 downto 0);`	`i_data : in std_logic_vector(7 downto 0);`
`o_data : out std_logic_vector(7 downto 0) --data returned up to 2 clock cycles after read_enable`	`o_data : out std_logic_vector(7 downto 0) --data returned up to 2 clock cycles after read_enable`
`);`	`);`